What is a Latency:
is amount of data that can be in flight at the same time (Little’s Law)
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
is time for a single access – Main memory latency is usually >> than processor cycle time
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
n loop iterations
subroutine call
vector access
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Cache HIT:
No Write Allocate, Write Allocate
Write Through, Write Back
Cache MISS:
Average Memory Access Time is equal:
Hit Time * ( Miss Rate + Miss Penalty )
Hit Time - ( Miss Rate + Miss Penalty )
Hit Time / ( Miss Rate - Miss Penalty )
Hit Time + ( Miss Rate * Miss Penalty )
Compulsory -
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
first-reference to a block, occur even with infinite cache
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
Capacity -
Conflict -
Algorithm for Cache HIT:
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
Algorithm for Cache MISS:
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
The formula of “Iron Law” of Processor Performance:
time/program = instruction/program * cycles/instruction * time/cycle
time/program = instruction/program * cycles/instruction + time/cycle
time/program = instruction/program + cycles/instruction * time/cycle
Structural Hazard:
An instruction depends on a data value produced by an earlier instruction
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Data Hazard:
Control Hazard:
What is a Bandwidth:
a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
What is a Bandwidth-Delay Product:
What is Computer Architecture?
the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
Least Recently Used (LRU):
FIFO with exception for most recently used block(s)
Used in highly associative caches
cache state must be updated on every access
Cache Hit -
Write Through – write both cache and memory, generally higher traffic but simpler to design
write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
No Write Allocate – only write to main memory
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
None of them
If cache size is doubled, miss rate usually drops by about √2
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Exploit temporal locality:
by remembering the contents of recently accessed locations
by fetching blocks of data around recently accessed locations
Exploit spatial locality:
What is the access time?
Describes the technology inside the memory chips and those innovative, internal organizations
Time between when a read is requested and when the desired word arrives
The minimum time between requests to memory.
What is the cycle time?
The minimum time between requests to memory
The maximum time between requests to memory.
What does SRAM stands for?
System Random Access memory
Static Random Access memory
Short Random Accessmemory
What does DRAM stands for?
Dataram Random Access memory
Dual Random Access memory
Dynamic Random Access memory
What does DDR stands for?
Double data reaction
Dual data rate
Double data rate
What is kernel process?
Provide at least two modes, indicating whether the running process is a user process or an operating system process
Provide a portion of the processor state that a user process can use but not write
Provide at least five modes, indicating whether the running process is a user process or an operating system process
Which one is NOT concerning to pitfall?
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
Simulating enough instructions to get accurate performance measures of the memory hierarchy
Predicting cache performance of one program from another
Over emphasizing memory bandwidth in DRAMs
Which one is concerning to fallacy?
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
The time from the reception of the response until the user begins to enter the next command
The time between when the user enters the command and the complete response is displayed
The time for the user to enter the command
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Average time per task in the queue
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Average length of queue
Average number of tasks in service
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
How many issue queue used in Centralized Superscalar 2 and Exceptions?
4
3
2
1
How many issue queue used in Distributed Superscalar 2 and Exceptions:
How many instructions used in Distributed Superscalar 2 and Exceptions?
Which of the following formula is true about Issue Queue for “Instruction Ready”:
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
What is a ARF:
Architectural Register File
Architecture Relocation File
Architecture Reload File
Architectural Read File
What is a ROB?
Read Only Buffer
Reorder Buffer
Reload Buffer
Recall Buffer
What is a FSB?
Finished Star Buffer
Finished Stall Buffer
Finished Store Buffer
Finished Stack Buffer
What is a PRF?
Pure Register File
Physical Register File
Pending Register File
Pipeline Register File
What is a SB?
Scalebit
Scaleboard
Scorebased
Scoreboard
How many stages used in Superscalar (Pipeline)?
5
6
7
What is about Superscalar means “F-D-X-M-W”?
Fetch, Decode, Instruct, Map, Write
Fetch, Decode, Execute, Memory, Writeback
Fetch, Decode, Excite, Memory, Write
Fetch, Decode, Except, Map, Writeback
Speculating on Exceptions “Prediction mechanism” is -
Only write architectural state at commit point, so can throw away partially executed instructions after exception
Exceptions are rare, so simply predicting no exceptions is very accurate
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
Speculating on Exceptions “Check prediction mechanism” is -
The way in which an object is accessed by a subject
Speculating on Exceptions “Recovery mechanism” is
An entity capable of accessing objects
What is a RT?
Rename Table
Recall Table
Relocate Table
Remove Table
What is a FL?
Free Launch
Free List
Free Leg
Free Last
What is an IQ?
Internal Queue
Instruction Queue
Issue Queue
Interrupt Queue
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Width and Height
Width and Lifetime
Time and Cycle
Length and Addition
Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Register name
Instruction cache
Data tags
Data cache
Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Integer Datapath
CLK
Address Queue
What is “VLIW”?
Very Less Interpreter Word
Very Long Instruction Word
Very Light Internal Word
Very Low Invalid Word
At VLIW by “performance and loop iteration” which time is longer?
Loop Unrolled
Software Pipelined
At VLIW by “performance and loop iteration” which time is shorter?
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Hardware to check pointer hazards
Speculative operations that don’t cause exceptions
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
What is an ALAT? :
Advanced Load Address Table
Allocated Link Address Table
Allowing List Address Table
Addition Long Accessibility Table
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Allow one instruction to branch multiple directions
What is a Compulsory?
cache is too small to hold all data needed by program, occur even under perfect replacement policy
misses that occur because of collisions due to less than full associativity
What is a Capacity?
What is a Conflict?
In Multilevel Caches “Local miss rate” equals =
misses in cache / accesses to cache
misses in cache / CPU memory accesses
misses in cache / number of instructions
In Multilevel Caches “Global miss rate” equals =
In Multilevel Caches “Misses per instruction” equals =
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
CPU time-Cache Miss-Miss Penalty-CPU time
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
What does mean MSHR?
Miss Status Handling Register
Map Status Handling Reload
Mips Status Hardware Register
Memory Status Handling Register
What does MAF?
Miss Address File
Map Address File
Memory Address File
At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
0,1,2,3,4,5,6,7
3,4,5,6,7,0,1,2
At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first “Order of fill”:
Storage Systems, “Larger block size to reduce miss rate”
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
The obvious way to reduce capacity misses is to increase cache capacity
Obviously, increasing associativity reduces conflict misses
Storage Systems, “Bigger caches to reduce miss rate” -
Storage Systems, “Higher associativity to reduce miss rate” -
In Non-Blocking Caches what does mean “Critical Word First”?
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
In Non-Blocking Caches what does mean “Early restart”?
A virus classification by target includes the following categories, What is a File infector?
A typical approach is as follows
Infects files that the operating system or shell consider to be executable
The key is stored with the virus
Far more sophisticated techniques are possible
What is a RAID 0?
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
Also called mirroring or shadowing, there are two copies of every piece of data
This organization was inspired by applying memory-style error correcting codes to disks
What is a RAID 1?
What is a RAID 2?
What is a RAID 3?
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
Many applications are dominated by small accesses
What is a RAID 4?
At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”? :
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Faults in software (usually) and hardware design (occasionally)
Mistakes by operations and maintenance personnel
At storage systems Gray and Siewiorek classify faults what does mean “Design faults”? :
At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”? :
At storage systems Gray and Siewiorek classify faults what does mean “Environmental faults”? :
Fire, flood, earthquake, power failure, and sabotage
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” - ? :
How many size of Cache L1 is true approximately? :
8 KB
256 KB
2 MB
How many size of Cache L2 is true approximately?
4 KB
32 MB
How many size of Cache L3 is true approximately?
3 MB
256 MB
How many main levels of Cache Memory?
8
What is a “Synchronization” in Cache Memory?
Execution or waiting for synchronization variables
Execution in the OS that is neither idle nor in synchronization access
Execution in user code
What is a “Kernel” in Cache Memory?
Network performance depends of what?
performance of swithes and transmission system
performance of switches
performance of transmission system
has no dependensies
The time between the start and the completion of an event ,such as milliseconds for a disk access is...
latency
bandwidth
throughput
performance
Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Learning curve itself is best measured by change in...
yeld
bytes
bits
seconds
Products that are sold by multiple vendors in large volumes and are essentialy identical
commodities
boxes
folders
files
Integrated circuit processes are charecterized by the
feature size
permanent size n
compex size
fixed size
For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
dynamic power
physical energy
constant supply
simple battery
Manufacturing costs that decrease over time are ____
the learning curve
the cycled line
the regular option
the final loop
Volume is a ________ key factor in determining cost
second
first
fifth
third
The most companies spend only ____________ of their income on R&D, which includes all engineering.
4% to 12%
15% to 30%
1% to 17%
30% to 48%
Systems alternate between two states of service with respect to an SLA:
1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
Desktop benchmarks divide into __ broad classes:
two
three
four
five
What MTTF means:
mean time to failure
mean time to feauture
mean this to failure
my transfers to failure
A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
90% 10%
50% 50%
70% 30%
89% 11%
(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Speedup
Efficiency
Probability
Ration
Which of the following descriptions corresponds to static power?
Grows proportionally to the transistor count (whether or not the transistors are switching)
Proportional to the product of the number of switching transistors and the switching rate Probability
Proportional to the product of the number of switching transistors and the switching rate
All of the above
Which of the following descriptions corresponds to dynamic power?
Certainly a design concern
None of the above
Which of the written below is NOT increase power consumption?
Increasing multithreading
Increasing performance
Increasing multiple cores
Increasing multithreading (V baze tak napisano)
Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
The number of transistors switching will be proportional to the sustained rate
The performance is proportional to the peak issue rate
If we want to sustain four instructions per clock
We must fetch more, issue more, and initiate execution on more than four instructions
We must fetch less, issue more, and initiate execution on more than two instructions
We must fetch more, issue less, and initiate execution on more than three instructions
We must fetch more, issue more, and initiate execution on less than five instructions
If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Static power
Dynamic power
Processing rate
Processor state
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Achievable ILP with software resource constraints
Limited ILP due to software dependences
Achievable ILP with hardware resource constraints
Variability of ILP due to software and hardware interaction
What is a hash table?
Popular data structure for organizing a large collection of data items so that one can quickly answer questions
Popular data structure for updating large collections, so that one can hardly answer questions
Popular tables for organizing a large collection of data structure
Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
Which of these is NOT characteristics of recent highperformance microprocessors?
Color
Power
Functional unit capability
Clock rate
How this process called: “Operations execute as soon as their operands are available”
data flow execution
instruction execution
data control execution
instruction field execution
For what the reorder buffer is used :
To pass results among instructions that may be speculated
To pass parameters through instructions that may be speculated
To get additional registers in the same way as the reservation stations
To control registers
How many fields contains the entry in the ROB:
Choose correct fields of entry in the ROB:
the instruction type, the destination field, the value field, and the ready field
the source type, the destination field, the value field, and the ready field
the program type, the ready field, the parameter field, the destination field
the instruction type, the destination field, and the ready field
Choose the steps of instruction execution:
issue, execute, write result, commit
execution, commit, rollback
issue, execute, override, exit
begin, write, interrupt, commit
Which one is not the major flavor of Multiple-issue processors
statistically superscalar processors
dynamically scheduled superscalar processors
statically scheduled superscalar processors
VLIW (very long instruction word) processors
Which Multiple-issue processors has not the hardware hazard detection
EPIC
Superscalar(dynamic)
Superscalar(static)
Superscalar(speculative)
Examples of EPIC:
Itanium
Pentium 4, MIPS R12K, IBM, Power5
MIPS and ARM
TI C6x
Examples of superscalar(static):
Examples of superscalar(dynamic) :
None at the present
Examples of VLIW/LIW:
A branch-prediction cache that stores the predicted address for the next instruction after a branch
branch-target buffer
data buffer
frame buffer
optical buffer
Buffering the actual target instructions allows us to perform an optimization which called:
branch folding
Branch prediction
Target instructions
Target address
Which is not the function of integrated instruction fetch unit:
Instruction memory commit
Integrated branch prediction
Instruction prefetch
Instruction memory access and buffering
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Address aliasing prediction
Dynamic branch prediction
How to decrypt RISC?
Reduced Instruction Set Computer
Recall Instruction Sell Communication
Rename Instruction Sequence Corporation
Red Instruction Small Computer
The ideal pipeline CPI is a measure of …
the maximum performance attainable by the implementation
the maximum performance attainable by the instruction
the minimum performance attainable by the implementation
the minimum performance attainable by the instruction
What is the Pipeline CP = ?
deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
deal pipeline CPU + Data hazard stalls + Control stalls
deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
Structural stalls + Data hazard stalls + Control stalls
The simplest and most common way to increase the ILP is …?
to exploit parallelism among iterations of a loop
to exploit minimalism among iterations of a loop
to destroy iterations of a loop
to decrease the minimalism of risk
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
loop-level parallelism
exploit-level parallelism
high-level minimalism
low-level minimalism
In parallelism have three different types of dependences, tagging him:
data dependences , name dependences , and control dependences
data dependences , name dependences , and surname dependences
datagram dependences , name dependences , and animal dependences
no correct answers
What is Name dependence?
name dependence occurs when two instructions use the same register or memory location
name dependence occurs when five or more instructions use the same register or memory location
name dependence occurs when instructions use the same name
All answers is correct
When occurs an output dependence?
When i and instruction j write the same register or memory location
when i and instruction j write the same name
when i and instruction j write the same adress or memory location
What is RAW (read after write)?
when j tries to read a source before i writes it, so j incorrectly gets the old value
when i tries to read a source before j writes it, so j correctly gets the old value
when j tries to write a source before i writes it
when a tries to write a source before b read it, so a incorrectly gets the old value
What is given is not a hazard?
RAR
WAR
WAW
LOL
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
loop unrolling
loop-level
loop rolling
Effect that results from instruction scheduling in large code segments is called…?
register pressure
registration
The simplest dynamic branch-prediction scheme is a
branch-prediction buffer
branch buffer
All answers correct
Branch predictors that use the behavior of other branches to make a prediction are called
correlating predictors or two-level predictors
branch table
three level loop
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
the number of prediction entries selected by the branch = 1K.
the number of prediction entries selected by the branch = 2K.
the number of prediction entries selected by the branch = 8K.
the number of prediction entries selected by the branch = 4K.
What is the compulsory in Cs model?
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
The number of accesses that miss divided by the number of accesses.
What is capacityin Cs model?
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
What is conflict in Cs model?
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
Choose the benefit of Cache Optimization.
Larger block size to reduce miss rate
Bigger caches to increase miss rat
Single level caches to reduce miss penalty
Choose the strategy of Seventh Optimization.
Critical word first
Critical restart
Sequential inter leaving
Merging Write Buffer to Reduce Miss Penalty
Choose the Eight Optimization
Nonblocking Caches to Increase Cache Bandwidth
Trace Caches to Reduce Hit Time
Choose the Eleventh Optimization
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
How much in percentage single-processor performance improvement has dropped to less than?
11%
22%
33%
How many elements of the Instruction Set Architecture (ISA):
What is the Thread Level Parallelism –
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
What is the PMD in computer classes?
Personal mobile device
Powerful markup distance
Percentage map device
What is the Instruction Level Parallelism:
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
How many elements in Trends of Technology?
What is the Vector Architecture and Graphic Processor Units (GPUs) –
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution
How many Optimizations’ in Cache memory Performance?
10
What is the Reducing the Miss Rate?
Time Optimization
Compiler Optimization
Performance Optimization
What is the Spatial Locality?
Exploit by fetching blocks of data around recently accessed locations
Exploit by remembering the contents of recently accessed locations
What is the Temporal Locality?
True formula of Module availability (MTTF – mean time to failure, MTTR – mean time to repair)?
MTTF / (MTTF + MTTR)
MTTF * (MTTF + MTTR)
MTTF * (MTTF - MTTR)
