Which of the following problems would NOT being identified during POST?
memory failure
bad monitor
bad video card
faulty CPU
In the figure below, Item D is the _______.
system board connections for IDE and floppy drives
DIMM slots
P1 power connection on the system board
PCI local bus slots
The correct order of the boot process is:
POST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
POST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
POST, OS configures the system and completes loading, User is able to execute application software
POST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS
What's the first thing the Startup BIOS looks for on a hard drive during boot up?
DOS Boot Record
Master Boot Record Correct
NT Boot Record
Piece of Pie
POST stands for:
partial operating system test
Power-off self test
Power-on self test
Pre-operational system test
None of the above
Which of the following is NOT a motherboard form factor:
ATX
Micro-PTX
LPX
BTX
AT
Which statement is NOT true about CMOS chips:
They maintain their settings long after you remove the CMOS battery
They generally hold between 64 bytes and 512 bytes of memory
They are sometimes referred to as NVRAM
They contain resource settings for plug-and-play devices in the ESCD
They contain the Real Time Clock that holds PC's time and date settings
How many of the following components are part of the CPU?
• ALU • Real Time Clock • branch predictor • Registers • Program Counter
1
2
3
4
5
Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?
Doubler and Tripler clocks
Derived System Clocks
Multiplier and Divider Clocks
Frequency Multiplexers
Which term is commonly used to reference the process of division and multiplication of the system clock to achieve the desired frequency?
Multiplier and Divider clocks
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
L1
L2
L3
L4
How many of the following items are true regarding cache? ◦ Cache uses DRAM with is faster that SRAM (found in main memory) ◦ Cache is not always found in the CPU ◦ Cache is designed as temporary storage for the CPU ◦ The size of cache is matched to be equal to the amount of main memory in the computer
0
Early Pentium CPUs are said to have multi-processing capabilities because they ____________
Can process data coming in while sending data out
Have the ability to exist with other processors
Use multiple registers
Contain two Arithmetic Logic Units Correct
Different speeds for computer components are achieved by using what is called ___________.
Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.
I/O Controller Hub
ISA bus
Graphics Memory Controller Hub
South Bridge
The amount of addressable memory is determined by the size of the address bus.
The Multiplier is the term used to describe the ________________
the ratio of the Backside Bus speed to the Memory Bus speed
the ratio of the Backside Bus speed to the CPU operating speed
the ratio of the CPU operating speed to the Front Side Bus speed
the ratio of the PCI bus speed to the Memory Bus speed
The front side bus connects the CPU to the ______.
coprocessor
L1 cache
system clock
memory bus
A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump
Control Unit
Branch Predictor
Hyper-Threading Technology
Cache
A unit that controls the operations of all components in the processor and executes conditional instructions
control unit
Instruction Register
ALU
Allows access to the hard disk drive, USB ports and other I/O devices
Program Counter
North Bridge
Allows access to the RAM and video card
West Bridge
East Bridge
A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel
Arithmetic Logic Unit
Superscalar Architecture
An internal memory location that contrains the instruction that is to be executed.
The part of the CPU that processes arithmetic and logical instructions
Floating Point Unit
Multiplier Bus
Divisor Programming Unit
An internal memory location that contains the address of the next instruction to be executed
Counting Register
Address Bus Architecture
Address Memory Unit
Used as temporary storage for the CPU
RAM
ROM
Hard Disk Drive
The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.
DMA Controller
IRQ Controller
Chipset
Super I/O
Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)
ISA
System
AGP
Memory
VESA-Local Bus
PCI
With 486 and higher CPUs, the cache controller is ________.
attached to the CMOS chip
not required, as the CPU itself controls the cache
housed on the system board
embedded in the CPU chip
Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.
Fast Bridge
ICH
Which of the following items relieves the CPU of processing traffic to and from all the buses and controllers on the system board?
The fast end of the Chipset Hub Architecture is still often referred to as the hub's ________.
How many of the following buses connect to the GMCH in the Accelerated Hub Architecture Chipset? •PCI • System • Memory • AGP • ISA • VESA-Local Bus
Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.
356
504
768
943
A SCSI chain must be terminated either by a passive, active or forced perfect terminator.
With IDE drives, the OS executes the remainder of the format process. This is known as a _____. Select one:
low level format
high-level format
partition
part
Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.
Which SCSI ID would usually be used for Hard Drives?
7
In a process called _____, track and sector markings are written on the hard drive at the factory.
high-level formatting
low level formatting
partitioning
parking
IDE drives use a _____-pin cable.
34
40
50
68
LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.
What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?
Parallel ATA
Serial ATA
Synchronous ATA
Single Mode ATA
Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.
Zone Bit Recording means ___________________
the number of sectors/track vary depending on the location of the track.
the tracks are arranged so the same number of sectors are used for all tracks.
each bit is recorded one zone at a time
a type of logical method of addressing larger capacity drives
Serial ports transmit data one byte at a time.
Which of the following is NOT a type of parallel port?
SPP
EPP
ECP
EDP
Parallel ports transmit data in parallel, _____ bit(s) at a time.
8
When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.
Normal
LBA
CHS
ECHS
Which of the following is true about SCSI vs EIDE?
EIDE is harder to set up than SCSI
SCSI is faster and more expensive
EIDE is faster and more expensive
SCSI is more popular than EIDE
The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?
504 MB
7.88 Gbits
128 GB
7.88 GB
In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.
adapter
ROM bios
CMOS chip
controller
The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.
actuators
heads
platters
spindles
A null-modem cable can be used to directly connect two ____ devices.
DTE
DCE
DCA
DMA
They contain resource settings for plug-and-play devices in the ESCD (Extended System Configuration Data) area
The contain the Real Time Clock that holds the PC’s time and date settings
Parallel ports are only able to transmit data in one direction at any given time.
Synchronous memory requires an external clock signal while Asynchronous does not.
How many of the following statements are true? ◦ DRAM is always faster that SRAM ◦ SRAM is lower cost that DRAM ◦ Both DRAM and SRAM are available in synchronous and asynchronous forms ◦ Both SRAM and DRAM retains values when the power is off
How many of the following statements are true? ◦ DRAM does not require refreshing to hold data ◦ SRAM allows for faster data access that DRAM ◦ SRAM costs more than DRAM per byte ◦ SRAM and DRAM memory cells are the same physical size per byte
How many of the following statements are true? ◦ ECC and non-ECC memory cost the same ◦ The parity bit in parity memory can be used to reconstruct bad data ◦ ECC memory allows for the correction of single bit errors ◦ Non-parity memory can detect and correct memory errors
Even
Odd
Which BUS version is set to replace AGP?
PCIe
Infiniband
PCI-X
With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.
Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.
What kind of Parity checking is being used if the following byte of data and it's parity bit are correct: Value: 1011 0111 Parity Bit: 1
even
equal
odd
balanced
Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.
PRAM, DRAM
SRAM, DRAM
DRAM, SRAM
SRAM, PRAM
What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?
Ram Timing Detect
Auto-Timing Detect
Serial Presence Detect
Memory Alert
Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.
You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?
1.6GB/s
2.1GB/s
3.2GB/s
1.06GB/s
One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.
checksum
bit parity
ESCD
PRAM
What type of bus is displayed in the figure below
16-bit ISA
VESA
8-bit ISA
The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus. (HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)
6,3
3,6
5,3
5,4
Which of the following is a list of expansion bus types ?
MCA, PCI, Memory
ISA, EISA
ISA, PCD, AGD
PCI, DIMM, SIMM
The ______ ISA bus was so named because it had only an eight-bit data path.
4-bit
8-bit
16-bit
32-bit
ECC may be present on DIMM module, and correct single bit errors when possible.
DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.
Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.
All data stored in _____ is lost when the power is turned off.
CMOS
On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)
2.1 GB/s
1.6 GB/s
500 MB/s
3.2 GB/s
The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.
S-100
EISA
ECC RAM differs from parity and nonparity RAM in that it can ______.
retain data when the power is removed
detect errors
automatically save data to the hard drive
detect and potentially correct errors
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