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CSA IITU Part 1 (235)

Beschreibung

Quiz am CSA IITU Part 1 (235), erstellt von Hello World am 20/12/2017.
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Zusammenfassung der Ressource

Frage 1

Frage
130. How many bytes equals Petabyte (PB)?
Antworten
  • · Quadrillion
  • · Million
  • · Trillion
  • · Billion
  • · 1000

Frage 2

Frage
129. Which one of the following is a memory whose duty is to store most frequently used data?
Antworten
  • · Main memory
  • · Cache
  • · ROM
  • · Auxiliary memory
  • · PROM

Frage 3

Frage
128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
Antworten
  • · Binary Adder
  • · Full Adder
  • · Half Adder
  • · Adder
  • · OR gate

Frage 4

Frage
127. The key technology used in IV generation computers is ___.
Antworten
  • · MSI
  • · SSI
  • · LSI & VLSI
  • · Transistors
  • · Vacuum Tubes

Frage 5

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126. The computer architecture having stored program is ___.
Antworten
  • · Harvard
  • · Von Neumann
  • · Pascal
  • · Ada
  • · Cobol

Frage 6

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125. Stack is a ___list.
Antworten
  • · FIFO
  • · LIFO
  • · FILO
  • · OFLI

Frage 7

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124. CACHE memory is implemented using ___.
Antworten
  • · Dynamic RAM
  • · Static RAM
  • · EA RAM
  • · ED RAM
  • · EP RAM

Frage 8

Frage
123. What does D stand for in a D flip-flop?
Antworten
  • · Direct
  • · Don’t care
  • · Data
  • · Device
  • · Disk

Frage 9

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104. What is a Capacity?
Antworten
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · first-reference to a block, occur even with infinite cache
  • · misses that occur because of collisions due to less than full associativity

Frage 10

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103. What is a Compulsory?
Antworten
  • · first-reference to a block, occur even with infinite cache
  • · cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • · misses that occur because of collisions due to less than full associativity

Frage 11

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39. 74. How many elements of the Instruction Set Architecture (ISA)
Antworten
  • 8
  • 7
  • 6

Frage 12

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38. 73. What is the MISD one of the categories of computers?
Antworten
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Set Data Stream

Frage 13

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36. 72. What is the Instruction Level Parallelism
Antworten
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Frage 14

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35. 71. What is the Request Level Parallelism
Antworten
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Frage 15

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34. 70. What is the Thread Level Parallelism
Antworten
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Frage 16

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33. 69. What is the Vector Architectures and Graphic Processor Units (GPUs)
Antworten
  • Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Frage 17

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32. 68. The Application of Brokerage operations how many cost of downtime per hour?
Antworten
  • 8.870.000$
  • 7.550.000$
  • 6.450.000$

Frage 18

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31. 67. What is the PMD in computer classes?
Antworten
  • Percentage map device
  • Personal mobile device
  • Peak maze development
  • Powerful markup distance

Frage 19

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30. 66. Which distance of price has Clusters/warehouse-scale computers?
Antworten
  • 100 – 100.000$
  • 100.000 – 200.000.000$
  • 5.000 – 10.000.000$

Frage 20

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29. 65. How many classes of computers classified?
Antworten
  • 7
  • 3
  • 5

Frage 21

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28. 64. What is the RLP?
Antworten
  • Request Level Parallelism
  • Research Level Parallelism
  • Random Level Parallelism

Frage 22

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27. 63. How much in percentage single-processor performance improvement has dropped to less than?
Antworten
  • 22%
  • 33%
  • 11%

Frage 23

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26. 62. When single-processor performance improvement has dropped?
Antworten
  • 2003
  • 2002
  • 2004

Frage 24

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25. 61. What is a RISC computers?
Antworten
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer
  • Reduced Instruction Set Computer

Frage 25

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24. 56. Choose the right formula of AMAT(в базе был неверный ответ можете попробовать подать апелляцию)
Antworten
  • Average Memory Access time = Hit Time + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
  • Average Memory Access time = Hit Time + Miss time * Miss penalty
  • Average Memory Access time = Hit Rate + Miss time * Miss penalty

Frage 26

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23. What is the total number of writes that hit in the cache?
Antworten
  • 588
  • 784
  • 12.5%
  • 0.25%

Frage 27

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22. 30. Definition of Block address:
Antworten
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • time to access upper level
  • memory closer to processor

Frage 28

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20. 28. Definition of Block:
Antworten
  • minimum unit that is presented or not present
  • location of block in memory
  • percentage of item not found in upper level
  • memory closer to processor
  • time to access upper level

Frage 29

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19. 27. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
Antworten
  • SRAM
  • DRAM
  • RAM

Frage 30

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18. 26. Performance of a machine is determined by:
Antworten
  • Instruction count, Clock cycle time, Correlating predictors
  • Instruction count, Clock cycle time, Clock cycle per instruction
  • Clock cycle time, Correlating predictors, Aggressive instruction
  • Clock cycle time, Clock cycles per instruction, Correlating Predictors

Frage 31

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17. 25. Pipe-lining is a unique feature of ___.
Antworten
  • CISC
  • IANA
  • ISA
  • RISC

Frage 32

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16. 24. The iconic feature of the RISC machine among the following are
Antworten
  • Increased memory size
  • Reduced number of addressing modes
  • Having a branch delay slot
  • All of the above

Frage 33

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15. 23. The Sun micro systems processors usually follow ___ architecture.
Antworten
  • CISC
  • ISA
  • ULTRA SPARC
  • RISC

Frage 34

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14. 22. Of the following, identify the memory usually written by the manufacturer.
Antworten
  • RAM
  • DRAM
  • SRAM
  • ROM
  • Cache Memory

Frage 35

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13. 21. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
Antworten
  • Hit rate
  • Miss rate
  • Access rate
  • Success rate

Frage 36

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12. 20. How many instructions can be implemented in MIPS?
Antworten
  • 2 clock cycles
  • 3 clock cycles
  • 4 clock cycles
  • 5 clock cycles

Frage 37

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19. The secondary effect that results from instruction scheduling in large code segments is called ___?
Antworten
  • Aggressive instruction
  • Correlating predictors
  • Register predictors
  • Register pressure

Frage 38

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10. 18. The CISC stands for?
Antworten
  • Computer Instruction Set Compliment
  • Complete Instruction Set Compliment
  • Computer Indexed Set Components
  • Complex Instruction Set Computer

Frage 39

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9. Assembly line operation is also called as?
Antworten
  • Pipelining process
  • Superscalar operation
  • None of the mentioned
  • Von Neumann cycle

Frage 40

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8. 16. Can you solve the Dining Philosophers’ Problem using monitors?
Antworten
  • Yes
  • No
  • Yes, but only if there are less than five philosophers
  • No, unless there are more than five philosophers

Frage 41

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7. 15. The central themes of operating system design are all concerned with the management of processes and threads?
Antworten
  • Multiprogramming, multiprocessing, distributed processing
  • Multitasking, multiprogramming, multithreading
  • Multiprocessing, uniprocessing, multitasking
  • Multithreading, distributed processing, uniprocessing

Frage 42

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6. 14. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Antworten
  • Availability, confidentiality, data integrity, authenticity
  • Safety, accountability, reliability, density
  • Usability, integrity, confidentiality, reliability
  • Flexibility, availability, accountability, authenticity

Frage 43

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5. 13. Which of the following principles has Deadlock?
Antworten
  • Execution, Association, Starvation
  • Prevention, Avoidance, Detection
  • Starvation, Detection, Exclusion
  • Exclusion, Avoidance, Starvation

Frage 44

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4. 12. How many principles has Deadlock?
Antworten
  • 3
  • 5
  • 2
  • 6

Frage 45

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3. 11. Three techniques are possible for I/O operations:
Antworten
  • Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
  • Machine I/O, Architecture I/O, Hardware I/O
  • Object-oriented I/O, Design I/O, Usable I/O
  • Control I/O, Status I/O, Transfer I/O

Frage 46

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2. 10. Cache Design has these properties?
Antworten
  • Size, search function, write function, read policy, vector algorithm
  • Size, mapping algorithm, vector function, write policy, replacement function
  • Size, blocking algorithm, search function, replacement vector, read policy
  • Size, block size, mapping function, replacement algorithm, write policy

Frage 47

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1. In Memory Hierarchy, at the Inboard storage which of the following are included:
Antworten
  • Magnetic disk
  • Magnetic tape
  • Optical disk
  • Main memory

Frage 48

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180. In Memory Hierarchy, at the Off-line storage which of the following are included:
Antworten
  • • Cache
  • • Magnetic disk
  • • Magnetic tape
  • • Main memory

Frage 49

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179. In Memory Hierarchy, at the Outboard storage which of the following are included:
Antworten
  • • Cache
  • • Main memory
  • • Magnetic tape
  • • Magnetic disk

Frage 50

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178. How many parts of Memory Hierarchy?
Antworten
  • • 5
  • • 4
  • • 2
  • • 3

Frage 51

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177. Which one is concerning to fallacy?
Antworten
  • o Predicting cache performance of one program from another
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs

Frage 52

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176. Which one is NOT concerning to pitfall?
Antworten
  • o Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • o Over emphasizing memory bandwidth in DRAMs
  • o Predicting cache performance of one program from another

Frage 53

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175. ChoosetheEleventhOptimization
Antworten
  • o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • o None of them

Frage 54

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174. ChoosetheEightOptimization
Antworten
  • o Merging Write Buffer to Reduce Miss Penalty
  • o Critical word first
  • o Nonblocking Caches to Increase Cache Bandwidth
  • o Trace Caches to Reduce Hit Time

Frage 55

Frage
173. Choose the strategy of Seventh Optimization.
Antworten
  • o Critical restart
  • o Critical word first
  • o Sequential inter leaving
  • o Merging Write Buffer to Reduce Miss Penalty

Frage 56

Frage
172. Choose the benefit of Cache Optimization.
Antworten
  • o Larger block size to reduce miss rate
  • o Bigger caches to increase miss rat
  • o Single level caches to reduce miss penalty
  • o None of them

Frage 57

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171. What is conflict in Cs model?
Antworten
  • o If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o None of them

Frage 58

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170. What is capacityin Cs model?
Antworten
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them

Frage 59

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169. What is the compulsory in Cs model?
Antworten
  • o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • o The number of accesses that miss divided by the number of accesses.
  • o None of them
  • o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Frage 60

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168. How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Antworten
  • o the number of prediction entries selected by the branch = 1K.
  • o the number of prediction entries selected by the branch = 2K.
  • o the number of prediction entries selected by the branch = 8K.
  • o the number of prediction entries selected by the branch = 4K.

Frage 61

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167. Branch predictors that use the behavior of other branches to make a prediction are called
Antworten
  • o correlating predictors or two-level predictors
  • o branch-prediction buffer
  • o branch table
  • o three level loop

Frage 62

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166. The simplest dynamic branch-prediction scheme is a
Antworten
  • o branch-prediction buffer
  • o branch buffer
  • o All answers correct
  • o registrationo registration

Frage 63

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165. Effect that results from instruction scheduling in large code segments is called…?
Antworten
  • o register pressure
  • o loop unrolling
  • o loop-level
  • o registration

Frage 64

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164. A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Antworten
  • o loop unrolling
  • o RAR
  • o loop-level
  • o loop rolling

Frage 65

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163. What is given is not a hazard?
Antworten
  • o RAR
  • o WAR
  • o WAW
  • o LOL

Frage 66

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162. What is RAW (read after write)?
Antworten
  • o when j tries to read a source before i writes it, so j incorrectly gets the old value
  • o when j tries to write a source before i writes it
  • o when i tries to read a source before j writes it, so j correctly gets the old value
  • o when a tries to write a source before b read it, so a incorrectly gets the old value

Frage 67

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161. When occurs an output dependence?
Antworten
  • o When i and instruction j write the same register or memory location
  • o when i and instruction j write the same adress or memory location
  • o when i and instruction j write the same name
  • o All answers is correct

Frage 68

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160. What is Name dependence?
Antworten
  • o name dependence occurs when two instructions use the same register or memory location
  • o name dependence occurs when five or more instructions use the same register or memory location
  • o name dependence occurs when instructions use the same name
  • o All answers is correct

Frage 69

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159. In parallelism have three different types of dependences, tagging him:
Antworten
  • o data dependences , name dependences , and surname dependences
  • o datagram dependences , name dependences , and animal dependences
  • o no correct answers
  • o data dependences , name dependences , and control dependences

Frage 70

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158. The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Antworten
  • o loop-level parallelism
  • o exploit-level parallelism
  • o high-level minimalism
  • o low-level minimalism

Frage 71

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157. The simplest and most common way to increase the ILP is …?
Antworten
  • o to exploit parallelism among iterations of a loop
  • o to exploit minimalism among iterations of a loop
  • o to destroy iterations of a loop
  • o to decrease the minimalism of risk

Frage 72

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156. What is the Pipeline CP = ?
Antworten
  • o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • o deal pipeline CPU + Data hazard stalls + Control stalls
  • o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
  • o Structural stalls + Data hazard stalls + Control stalls

Frage 73

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155. The ideal pipeline CPI is a measure of …
Antworten
  • o the maximum performance attainable by the implementation
  • o the maximum performance attainable by the instruction
  • o the minimum performance attainable by the implementation
  • o the minimum performance attainable by the instruction

Frage 74

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154. How to decrypt RISC?
Antworten
  • o Reduced Instruction Set Computer
  • o Recall Instruction Sell Communication
  • o Rename Instruction Sequence Corporation
  • o Red Instruction Small Computer

Frage 75

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153. What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Antworten
  • o Address aliasing prediction
  • o Branch prediction
  • o Integrated branch prediction
  • o Dynamic branch prediction

Frage 76

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152. Which is not the function of integrated instruction fetch unit:
Antworten
  • o Instruction memory commit
  • o Integrated branch prediction
  • o Instruction memory access and buffering
  • o Instruction prefetch

Frage 77

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151. Buffering the actual target instructions allows us to perform an optimization which called:
Antworten
  • o branch folding
  • o Branch prediction
  • o Target instructions
  • o Target address

Frage 78

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150. A branch-prediction cache that stores the predicted address for the next instruction after a branch
Antworten
  • o branch-target buffer
  • o data buffer
  • o frame buffer
  • o optical buffer

Frage 79

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149. Examples of VLIW/LIW:
Antworten
  • o TI C6x
  • o MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5

Frage 80

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148. Examples of superscalar(dynamic) :
Antworten
  • o None at the present
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o MIPS and ARM
  • o TI C6x

Frage 81

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147. Examples of superscalar(static):
Antworten
  • • MIPS and ARM
  • o Itanium
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Frage 82

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146. Examples of EPIC:
Antworten
  • o Itanium
  • o MIPS and ARM
  • o Pentium 4, MIPS R12K, IBM, Power5
  • o TI C6x

Frage 83

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145. Which Multiple-issue processors has not the hardware hazard detection:
Antworten
  • o EPIC
  • o Superscalar(dynamic)
  • o Superscalar(static)
  • o Superscalar(speculative)

Frage 84

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144. Which one is not the major flavor of Multiple-issue processors:
Antworten
  • o statistically superscalar processors
  • o dynamically scheduled superscalar processors
  • o statically scheduled superscalar processors
  • o VLIW (very long instruction word) processors

Frage 85

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143. Choose the steps of instruction execution:
Antworten
  • o issue, execute, write result, commit
  • o execution, commit, rollback
  • o issue, execute, override, exit
  • o begin, write, interrupt, commit

Frage 86

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142. Choose correct fields of entry in the ROB:
Antworten
  • o the instruction type, the destination field, the value field, and the ready field
  • o the source type, the destination field, the value field, and the ready field
  • o the program type, the ready field, the parameter field, the destination field
  • o the instruction type, the destination field, and the ready field

Frage 87

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141. How many fields contains the entry in the ROB:
Antworten
  • 4
  • 6
  • 5
  • 3

Frage 88

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140. For what the reorder buffer is used :
Antworten
  • o To pass parameters through instructions that may be speculated
  • o To pass results among instructions that may be speculated.
  • o To get additional registers in the same way as the reservation stations
  • o To control registers

Frage 89

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139. How this process called: “Operations execute as soon as their operands are available”
Antworten
  • o data flow execution
  • o data control execution
  • o instruction execution
  • o instruction field execution

Frage 90

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138. Which of these is NOT characteristics of recent highperformance microprocessors?
Antworten
  • o Color
  • o Functional unit capability
  • o Clock rate
  • o Power

Frage 91

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• Popular data structure for organizing a large collection of data items so that one can quickly
Antworten
  • o Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • o Popular tables for organizing a large collection of data structure
  • o Popular data structure for updating large collections, so that one can hardly answer questions
  • o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Frage 92

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136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Antworten
  • o Achievable ILP with software resource constraints
  • o Limited ILP due to software dependences
  • o Achievable ILP with hardware resource constraints
  • o Variability of ILP due to software and hardware interaction

Frage 93

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135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Antworten
  • o Dynamic power
  • o Processing rate
  • o Static power
  • o Processor state

Frage 94

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134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Antworten
  • o Static power
  • o Dynamic power
  • o Processing rate
  • o Processor state

Frage 95

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133. If we want to sustain four instructions per clock
Antworten
  • o We must fetch more, issue more, and initiate execution on more than four instructions
  • o We must fetch less, issue more, and initiate execution on more than two instructions
  • o We must fetch more, issue more, and initiate execution on less than five instructions
  • o We must fetch more, issue less, and initiate execution on more than three instructions

Frage 96

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132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
Antworten
  • o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
  • o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
  • o The number of transistors switching will be proportional to the sustained rate
  • o The performance is proportional to the peak issue rate

Frage 97

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131. Which of the written below is NOT increase power consumption?
Antworten
  • o Increasing multithreading
  • o Increasing performance
  • o Increasing multiple cores
  • o Increasing multithreading(повторяется хз что тут )

Frage 98

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130. Which of the following descriptions corresponds to dynamic power?
Antworten
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Certainly a design concern
  • o None of the above

Frage 99

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129. Which of the following descriptions corresponds to static power?
Antworten
  • o Grows proportionally to the transistor count (whether or not the transistors are switching)
  • o Proportional to the product of the number of switching transistors and the switching rate Probability
  • o Proportional to the product of the number of switching transistors and the switching rate
  • o All of the above

Frage 100

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128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Antworten
  • o Speedup
  • o Efficiency
  • o Probability
  • o Ration

Frage 101

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127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Antworten
  • • 90% 10%
  • o 70% 30%
  • o 50% 50%
  • o 89% 11%

Frage 102

Frage
126. What MTTF means:
Antworten
  • o mean time to failure
  • o mean time to feauture
  • o mean this to failure
  • o my transfers to failure

Frage 103

Frage
125. Desktop benchmarks divide into __ broad classes:
Antworten
  • o two
  • o three
  • o four
  • o five

Frage 104

Frage
124. Systems alternate between two states of service with respect to an SLA:
Antworten
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
  • o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Frage 105

Frage
123. The most companies spend only ____________ of their income on R&D, which includes all engineering.
Antworten
  • o 30% to 48%
  • o 4% to 12%
  • o 15% to 30%
  • o 1% to 17%

Frage 106

Frage
122. Volume is a ________ key factor in determining cost.
Antworten
  • o second
  • o first
  • o fifth
  • o third

Frage 107

Frage
121. Manufacturing costs that decrease over time are ____
Antworten
  • o the learning curve
  • o the cycled line
  • o the regular option
  • o the final loop

Frage 108

Frage
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
Antworten
  • o dynamic power
  • o physical energy
  • o constant supply
  • o simple battery

Frage 109

Frage
119. Integrated circuit processes are charecterized by the
Antworten
  • o feature size
  • o permanent size n
  • o compex size
  • o fixed size

Frage 110

Frage
118. Products that are sold by multiple vendors in large volumes and are essentialy identical
Antworten
  • o boxes
  • o files
  • o folders
  • o commodities

Frage 111

Frage
117. Learning curve itself is best measured by change in...
Antworten
  • o bytes
  • o bits
  • o seconds
  • o yeld

Frage 112

Frage
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Antworten
  • o bandwidth
  • o throughput
  • o latency
  • o performance

Frage 113

Frage
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Antworten
  • o bandwidth
  • o latency
  • o throughput
  • o performance

Frage 114

Frage
1. Network performance depends of what?
Antworten
  • o performance of swithes and transmission system
  • o performance of switches
  • o has no dependensies
  • o performance of transmission system

Frage 115

Frage
113. What is a “Kernel” in Cache Memory?
Antworten
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables
  • o Execution in user code

Frage 116

Frage
112. What is a “Synchronization” in Cache Memory?
Antworten
  • o Execution in user code
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution or waiting for synchronization variables

Frage 117

Frage
111. What is a “Kernel” in Cache Memory?
Antworten
  • o Execution or waiting for synchronization variables
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code

Frage 118

Frage
110. What is a “Synchronization” in Cache Memory?
Antworten
  • o Execution in the OS that is neither idle nor in synchronization access
  • o Execution in user code
  • o Execution or waiting for synchronization variables
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