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Quiz von Hello World, aktualisiert more than 1 year ago
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Erstellt von Hello World
vor mehr als 6 Jahre
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Frage 1
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109. What is a “Kernel” in Cache Memory?
Antworten
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o Execution in the OS that is neither idle nor in synchronization access
-
o Execution or waiting for synchronization variables
-
o Execution in user code
Frage 2
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108. What is a “Synchronization” in Cache Memory?
Antworten
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o Execution in the OS that is neither idle nor in synchronization access
-
o Execution in user code
-
o Execution or waiting for synchronization variables
Frage 3
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107. How many main levels of Cache Memory?
Antworten
-
3
-
2
-
6
-
8
Frage 4
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106. How many size of Cache L3 is true approximately? :
Antworten
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o 3 MB
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o 256 KB
-
o 256 MB
Frage 5
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105. How many size of Cache L2 is true approximately? :
Antworten
-
o 256 KB
-
o 4 KB
-
o 32 MB
Frage 6
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104. How many size of Cache L1 is true approximately? :
Antworten
-
o 8 KB
-
o 256 KB
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o 2 MB
Frage 7
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103. Little’s Law and a series of definitions lead to several useful equations for
Antworten
-
o Average length of queue
-
o Average number of tasks in service
Frage 8
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102. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Antworten
-
o Average number of tasks in service
-
o Average length of queue
Frage 9
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101. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Antworten
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
Frage 10
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100. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Antworten
-
o Average time per task in the queue
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 11
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99. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Antworten
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 12
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98. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Antworten
-
o The time from the reception of the response until the user begins to enter the next command
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
Frage 13
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97. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Antworten
-
o The time between when the user enters the command and the complete response is displayed
-
o The time for the user to enter the commando The time for the user to enter the command
-
o The time from the reception of the response until the user begins to enter the next command
Frage 14
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96. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” - ? :
Antworten
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
-
o The time from the reception of the response until the user begins to enter the next command
Frage 15
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95. At storage systems Gray and Siewiorek classify faults what does mean “Environmental faults”? :
Antworten
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o Fire, flood, earthquake, power failure, and sabotage
-
o Faults in software (usually) and hardware design (occasionally)
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Frage 16
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94. At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”? :
Antworten
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o Mistakes by operations and maintenance personnel
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
o Faults in software (usually) and hardware design (occasionally)
Frage 17
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93. At storage systems Gray and Siewiorek classify faults what does mean “Design faults”? :
Antworten
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o Faults in software (usually) and hardware design (occasionally)
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
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o Mistakes by operations and maintenance personnel
Frage 18
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92. At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”? :
Antworten
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o Faults in software (usually) and hardware design (occasionally)
-
o Mistakes by operations and maintenance personnel
-
o Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Frage 19
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91. What is a RAID 4?
Antworten
-
o Many applications are dominated by small accesses
-
o Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Frage 20
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90. What is a RAID 3?
Antworten
-
o Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
o Many applications are dominated by small accesses
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Frage 21
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89. What is a RAID 2?
Antworten
-
o This organization was inspired by applying memory-style error correcting codes to disks
-
o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
o Also called mirroring or shadowing, there are two copies of every piece of data
Frage 22
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88. What is a RAID 1?
Antworten
-
o Also called mirroring or shadowing, there are two copies of every piece of data
-
o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
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o This organization was inspired by applying memory-style error correcting codes to disks
Frage 23
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87. What is a RAID 0?
Antworten
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o It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
-
o Also called mirroring or shadowing, there are two copies of every piece of data
-
o This organization was inspired by applying memory-style error correcting codes to disks
Frage 24
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86. A virus classification by target includes the following categories, What is a File infector?
Antworten
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o Infects files that the operating system or shell consider to be executable
-
o A typical approach is as follows
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o The key is stored with the virus
-
o Far more sophisticated techniques are possible
Frage 25
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85. In Non-Blocking Caches what does mean “Early restart”?
Antworten
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o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
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o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Frage 26
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84. In Non-Blocking Caches what does mean “Critical Word First”?
Antworten
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o Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
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o Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Frage 27
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83. Storage Systems, “Higher associativity to reduce miss rate” -
Antworten
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o Obviously, increasing associativity reduces conflict misses
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o The obvious way to reduce capacity misses is to increase cache capacity
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o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Frage 28
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82. Storage Systems, “Bigger caches to reduce miss rate” -
Antworten
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o The obvious way to reduce capacity misses is to increase cache capacity
-
o Obviously, increasing associativity reduces conflict misses
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o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
Frage 29
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81. Storage Systems, “Larger block size to reduce miss rate” -
Antworten
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o The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
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o The obvious way to reduce capacity misses is to increase cache capacity
-
o Obviously, increasing associativity reduces conflict misses
Frage 30
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80. At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first “Order of fill”:
Antworten
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o 3,4,5,6,7,0,1,2
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o 0,1,2,3,4,5,6,7
Frage 31
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79. At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
Antworten
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o 0,1,2,3,4,5,6,7
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o 3,4,5,6,7,0,1,2
Frage 32
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78. What does MAF?
Antworten
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o Miss Address File
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o Map Address File
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o Memory Address File
Frage 33
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77. What does mean MSHR?
Antworten
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o Miss Status Handling Register
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o Map Status Handling Reload
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o Mips Status Hardware Register
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o Memory Status Handling Register
Frage 34
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76. Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
Antworten
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o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
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o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
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o CPU time-Cache Miss-Miss Penalty-CPU time
Frage 35
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75. Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Antworten
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o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
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o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
-
o CPU time-Cache Miss-Miss Penalty-CPU time
Frage 36
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74. Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
Antworten
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o CPU time-Cache Miss-Miss Penalty-CPU time
-
o CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
o CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Frage 37
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73. In Multilevel Caches “Misses per instruction” equals =
Antworten
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o misses in cache / number of instructions
-
o misses in cache / accesses to cache
-
o misses in cache / CPU memory accesses
Frage 38
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72. In Multilevel Caches “Global miss rate” equals =
Antworten
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o misses in cache / CPU memory accesses
-
o misses in cache / accesses to cache
-
o misses in cache / number of instructions
Frage 39
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71. In Multilevel Caches “Local miss rate” equals =
Antworten
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o misses in cache / accesses to cache
-
o misses in cache / number of instructions
-
o misses in cache / CPU memory accesses
Frage 40
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70. What is a Conflict?
Antworten
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o misses that occur because of collisions due to less than full associativity
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o first-reference to a block, occur even with infinite cache
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o cache is too small to hold all data needed by program, occur even under perfect replacement policy
Frage 41
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67. At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Antworten
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o Allow one instruction to branch multiple directions
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o Speculative operations that don’t cause exceptions
Frage 42
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66. What is an ALAT? :
Antworten
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o Advanced Load Address Table
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o Allocated Link Address Table
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o Allowing List Address Table
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o Addition Long Accessibility Table
Frage 43
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65. h Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Antworten
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o Hardware to check pointer hazards
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o Speculative operations that don’t cause exceptions
Frage 44
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64. At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Antworten
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o Speculative operations that don’t cause exceptions
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o Hardware to check pointer hazards
Frage 45
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63. At VLIW by “performance and loop iteration” which time is shorter?
Antworten
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o Software Pipelined
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o Loop Unrolled
Frage 46
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62. At VLIW by “performance and loop iteration” which time is longer?
Antworten
-
o Loop Unrolled
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o Software Pipelined
Frage 47
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61. What is “VLIW”?
Antworten
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o Very Long Instruction Word
-
o Very Light Internal Word
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o Very Less Interpreter Word
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o Very Low Invalid Word
Frage 48
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60. Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Antworten
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o Integer Datapath
-
o CLK
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o Free List
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o Address Queue
Frage 49
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59. Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Antworten
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o Register name
-
o Instruction cache
-
o Data tags
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o Data cache
Frage 50
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58. At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Antworten
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o Width and Lifetime
-
o Width and Height
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o Time and Cycle
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o Length and Addition
Frage 51
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57. What is an IQ?
Antworten
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o Issue Queue
-
o Internal Queue
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o Interrupt Queue
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o Instruction Queue
Frage 52
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56. What is a FL?
Antworten
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o Free List
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o Free Last
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o Free Launch
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o Free Leg
Frage 53
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55. What is a RT?
Antworten
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o Rename Table
-
o Recall Table
-
o Relocate Table
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o Remove Table
Frage 54
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54. Speculating on Exceptions “Recovery mechanism” is -
Antworten
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o Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o An entity capable of accessing objects
-
o None of them
Frage 55
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1. Speculating on Exceptions “Check prediction mechanism” is -
Antworten
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o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o The way in which an object is accessed by a subject
-
o None of them
Frage 56
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52. Speculating on Exceptions “Prediction mechanism” is -
Antworten
-
o Exceptions are rare, so simply predicting no exceptions is very accurate
-
o Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
o Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
o None of them
Frage 57
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51. What is about Superscalar means “F-D-X-M-W”?
Antworten
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o Fetch, Decode, Execute, Memory, Writeback
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o Fetch, Decode, Instruct, Map, Write
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o Fetch, Decode, Excite, Memory, Write
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o Fetch, Decode, Except, Map, Writeback
Frage 58
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50. How many stages used in Superscalar (Pipeline)?
Antworten
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5
-
4
-
6
-
7
Frage 59
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49. What is a SB?
Antworten
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o Scoreboard
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o Scorebased
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o Scalebit
-
o Scaleboard
Frage 60
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48. What is a PRF?
Antworten
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o Physical Register File
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o Pending Register File
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o Pipeline Register File
-
o Pure Register File
Frage 61
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47. What is a FSB?
Antworten
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o Finished Store Buffer
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o Finished Stack Buffer
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o Finished Stall Buffer
-
o Finished Star Buffer
Frage 62
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46. What is a ROB?
Antworten
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o Reorder Buffer
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o Read Only Buffer
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o Reload Buffer
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o Recall Buffer
Frage 63
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45. What is a ARF:
Antworten
-
o Architectural Register File
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o Architecture Relocation File
-
o Architecture Reload File
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o Architectural Read File
Frage 64
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44. Which of the following formula is true about Issue Queue for “Instruction Ready”:
Antworten
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o Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
-
o Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
-
o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
-
o Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
Frage 65
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43. How many instructions used in Distributed Superscalar 2 and Exceptions?
Antworten
-
4
-
3
-
2
-
1
Frage 66
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42. How many issue queue used in Distributed Superscalar 2 and Exceptions:
Antworten
-
4
-
3
-
2
-
1
Frage 67
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41. How many issue queue used in Centralized Superscalar 2 and Exceptions?
Antworten
-
4
-
3
-
2
-
1
Frage 68
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40. Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
Antworten
-
o Average length of queue
-
o Average number of tasks in service
Frage 69
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39. Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Antworten
-
o Average number of tasks in service
-
o Average length of queue
Frage 70
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38. Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Antworten
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
Frage 71
Frage
37. Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Antworten
-
o Average time per task in the queue
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 72
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36. Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Antworten
-
o Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
o Average time per task in the queue
-
o Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 73
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35. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Antworten
-
o The time from the reception of the response until the user begins to enter the next command
-
o The time for the user to enter the command
-
o The time between when the user enters the command and the complete response is displayed
Frage 74
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34. If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Antworten
-
o The time between when the user enters the command and the complete response is displayed
-
o The time for the user to enter the command
-
o The time from the reception of the response until the user begins to enter the next command
Frage 75
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33. What is kernel process?
Antworten
-
o Provide at least two modes, indicating whether the running process is a user process or an operating system process
-
o Provide at least five modes, indicating whether the running process is a user process or an operating system process
-
o Provide a portion of the processor state that a user process can use but not write
-
o None of them
Frage 76
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32. What does DDR stands for?
Antworten
-
o Double data rate
-
o Dual data rate
-
o Double data reaction
-
o None of them
Frage 77
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31. What does DRAM stands for?
Antworten
-
o Dynamic Random Access memory
-
o Dual Random Access memory
-
o Dataram Random Access memory
Frage 78
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30. What does SRAM stands for?
Antworten
-
o Static Random Access memory
-
o System Random Access memory
-
o Short Random Accessmemory
-
o None of them
Frage 79
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29. What is the cycle time?
Antworten
-
o The minimum time between requests to memory.
-
o Time between when a read is requested and when the desired word arrives
-
o The maximum time between requests to memory.
-
o None of them
Frage 80
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28. What is the access time?
Antworten
-
o Time between when a read is requested and when the desired word arrives
-
o The minimum time between requests to memory.
-
o Describes the technology inside the memory chips and those innovative, internal organizations
-
o None of them
Frage 81
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27. Data Hazard:
Antworten
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 82
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26. Structural Hazard:
Antworten
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o An instruction depends on a data value produced by an earlier instruction
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 83
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25. Exploit spatial locality:
Antworten
-
o by fetching blocks of data around recently accessed locations
-
o by remembering the contents of recently accessed locations
-
o None of them
Frage 84
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24. Exploit temporal locality:
Antworten
-
o by remembering the contents of recently accessed locations
-
o None of them
-
o by fetching blocks of data around recently accessed locations
Frage 85
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23. Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Antworten
-
o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
o If cache size is doubled, miss rate usually drops by about √2
-
o None of them
Frage 86
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22. Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Antworten
-
o If cache size is doubled, miss rate usually drops by about √2
-
o Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
o None of them
Frage 87
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21. Cache Hit -
Antworten
-
o Write Through – write both cache and memory, generally higher traffic but simpler to design
-
o write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
-
o No Write Allocate – only write to main memory
Frage 88
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20. Least Recently Used (LRU):
Antworten
-
o cache state must be updated on every access
-
o Used in highly associative caches
-
o FIFO with exception for most recently used block(s)
Frage 89
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19. What is Computer Architecture?
Antworten
-
o is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
-
o is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
-
o the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Frage 90
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18. What is a Bandwidth-Delay Product:
Antworten
-
o is amount of data that can be in flight at the same time (Little’s Law)
-
o is time for a single access – Main memory latency is usually >> than processor cycle time
-
o is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
Frage 91
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17. What is a Bandwidth:
Antworten
-
o a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
o is time for a single access – Main memory latency is usually >> than processor cycle time
-
o is amount of data that can be in flight at the same time (Little’s Law)
Frage 92
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16. Control Hazard:
Antworten
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Frage 93
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15. Data Hazard:
Antworten
-
o An instruction depends on a data value produced by an earlier instruction
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 94
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1. Structural Hazard:
Antworten
-
o An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
o An instruction depends on a data value produced by an earlier instruction
-
o Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 95
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13. The formula of “Iron Law” of Processor Performance:
Antworten
-
o time/program = instruction/program * cycles/instruction * time/cycle
-
o time/program = instruction/program * cycles/instruction + time/cycle
-
o time/program = instruction/program + cycles/instruction * time/cycle
Frage 96
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12. Algorithm for Cache MISS:
Antworten
-
o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
-
o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
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o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
Frage 97
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11. Algorithm for Cache HIT:
Antworten
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o Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
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o Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
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o Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache
Frage 98
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9. Capacity -
Antworten
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o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
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o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
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o first-reference to a block, occur even with infinite cache
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8. Compulsory -
Antworten
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o cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
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o first-reference to a block, occur even with infinite cache
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o misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
Frage 100
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7. Average Memory Access Time is equal:
Antworten
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o Hit Time * ( Miss Rate + Miss Penalty )
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o Hit Time - ( Miss Rate + Miss Penalty )
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o Hit Time / ( Miss Rate - Miss Penalty )
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o Hit Time + ( Miss Rate * Miss Penalty )
Frage 101
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6. Cache MISS:
Antworten
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o No Write Allocate, Write Allocate
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o Write Through, Write Back
Frage 102
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5. Cache HIT:
Antworten
-
o No Write Allocate, Write Allocate
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o Write Through, Write Back
Frage 103
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4. What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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o subroutine call
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o n loop iterations
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o vector access
Frage 104
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3. What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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o subroutine call
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o n loop iterations
-
o vector access
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2. What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Antworten
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o n loop iterations
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o subroutine call
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o vector access
Frage 106
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1. - What is a Latency:
Antworten
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o is time for a single access – Main memory latency is usually >> than processor cycle time
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o is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
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o is amount of data that can be in flight at the same time (Little’s Law)
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