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A branch-prediction cache that stores the predicted address for the next instruction after a branch
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branch target buffer
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data buffer
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optical buffer
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Buffering the actual target instructions allows us to perform an optimization which called:
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branch folding
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branch prediction
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target instructions
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target address
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Which is not the function of integrated instructions fetch unit:
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Instruction memory commit
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Integrated branch prediction
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Instruction prefetch
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Instruction memory access and buffering
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What is the simple technique that predict whether two stores or a load and a store refer to the same memory address:
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What is a topology in interconnection networks?
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It indicates how the nodes a network are organised
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It is the minimum distance between the farthest nodes in a network
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Number of edges connected with a node is called node degree
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What is a network diameter?
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It is the minimum distance between the farthest nodes in a network
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It indicates how the nodes a network are organised
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Number of edges connected with a node is called node degree
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What is a node degree?
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Number of edges connected with a node is called node degree
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It indicates how the nodes a network are organised
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It is the minimum distance between the farthest nodes in a network
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What is a bisection bandwidth?
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Number of edges required to be cut to divide a network into two halves is called bisection bandwidth
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It indicates how the nodes a network are organised
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It is the minimum distance between the farthest nodes in a network
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What is a network throughput?
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It indicates how the nodes a network are organised
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It is delay in transferring the message between two nodes
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It is indicative measure of the message carrying capacity of a network
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It is the minimum distance between the farthest nodes in a network
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What is a data routing functions?
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The functions which when executed establish the path between the source & destination
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It is indicative measure of the message carrying capacity of a network
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It is the minimum distance between the farthest nodes in a network
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What is a hardware cost?
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It indicates how the nodes a network are organised
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The data routing functions are the functions which when executed establish the path between the source and the destination
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It refers to the cost involved in the implementation of an interconnection network
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It is an indicative measure of the message carrying capacity of a network
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What is a blocking and non-blocking network?
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It indicates how the nodes a network are organized
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The data routing functions are the functions which when executed establish the path between the source and the destination
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network In non-blocking networks the route from any free input node to any free output node can always be provided
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It is and indicative measure of the message carrying capacity of a network
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Design issue of interconnection network?
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Software Cost
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Hardware Cost
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RLP
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Symmetry of the network
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Design issue of interconnection network (нет ответа в базе)
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What is the Message Size?
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It indicates how the nodes a network are organized
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The data routing functions are the functions which when executed establish the path between the source and the destination
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How much data a processor can send in one time unit
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It is and indicative measure of the message carrying capacity of a network
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What is a Data transfer time?
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It indicates how the nodes a network are organized
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The data routing functions are the functions which when executed establishe the path between the source and the destination
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How long does it take for a message to reach to another processor
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It is and indicative measure of the message carrying capacity of a network
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Select two-dimensional network (в какой то базе interconnection network)
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Mesh
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Linear Array
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Cross Bar
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Select multi-dimensional network (в какой то базе interconnection network)
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Linear Array
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Cross Bar
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Cube
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Select multi-dimensional network (в какой то базе interconnection network)
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Linear Array
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Cross Bar
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Hyper Cube
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Select non-blocking network (в какой то базе interconnection network)
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Linear Array
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Cube
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Cross Bar
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A modified version of the tree network (в какой то базе interconnection network)
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Fat tree
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Cube
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Linear Array
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A interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
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Systolic Array
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Cube
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Linear Array
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A _____________ interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
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Hyper cube
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Cube
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Linear array
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In computer architecture, __________ is the ability of central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system
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Multithreading
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Computing
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Array processing
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In computing, a __________ is a central processing unit(CPU) that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors compared to scalar processors, whose instructions operate in a single data items
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Multithreading
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Vector processes
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Computing
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Array processing
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A _________ is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behaviour of executing instructions in order
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Multithreading
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Branch
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Prediction
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Array processing
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A __________ is a digital circuit that tries to guess which way a branch (e.g. an if-then-else structure) will go before this is known for sure
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Multithreading
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Branch
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Branch Prediction
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________________ optimization technique where a computer system performs some task that may not be actually needed
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Multithreading
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Branch
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Speculative execution
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Select two-dimensional network
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Mesh
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Linear array
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Cross bar
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Single instruction, single data (SISD)
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only one instruction stream is being acted on by the CPU during any one clock cycle
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a type of parallel computer
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Currently the most common type of parallel computer - most modern supercomputers fall into this category
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In serial computing
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Multithreading instructions from each part execute simultaneously on different processors
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Instructions are executed sequentially one after another
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A problem is broken into discrete parts that can be solved concurrently
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In parallel computing
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Multithreading instructions from each part execute simultaneously on different processors
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Instructions are executed sequentially one after another
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A problem is broken into discrete parts that can be solved concurrently
Frage 33
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From a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
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A logically discrete section of computational work
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Breaking a task into steps performed by different processor units, with inputs streaming through much like an assembly line
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Massively parallel . . .
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From a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
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Refers to the hardware that comprises a given parallel system - having many processing elements
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Solving many similar but independent tasks simultaneously, little to no need for coordination between the tasks
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Embarrassingly parallel . . .
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From a strictly hardware point of view, describes a computer architecture where all processors have direct(usually bus based ) access to common physical memory
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Refers to the hardware that comprises a given parallel system - having many processing elements
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Solving many similar but independent tasks simultaneously, little to no need for coordination between the tasks
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Network performance depends of what?
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Which one is not the major flavor of Multiple-issue processors:
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statistically superscalar processors
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dynamically scheduled superscalar processors
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statically scheduled superscalar processors
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VLIW (very long instruction word) processors
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A _____________ interconnection network is an extension of cube network
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Hyper Cube
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Cube
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Linear Array
Frage 39
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Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
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A logically discrete section of computational work
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From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
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What is Personal mobile device (PMD)?
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A collection of wireless devices with multimedia user interfaces
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A collection of computers with wireless network adapters
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A collection of Clusters/Warehouse-scale computers
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Where the embedded microprocessors are used?
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What functions has Instruction Set Architecture (ISA)?
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Serves as the boundary between the software and hardware
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Serves as the bridge between CPU and Memory
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Serves as the bridge between CPU and Cache
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By Moore's law, growth rate in transistor count on a chip is doubling?
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every 8 to 12 months
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every 12 to 16 months
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every 18 to 24 months
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How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?
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What is the “Module reliability” in Dependability?
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a measure of the continuous service accomplishment from a reference initial instant
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a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
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a measure of the interruption
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What is response time?
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the time between the start and the completion of an event
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The time to get an information
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The time spent on execution of a program
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The guiding principle of reporting performance measurements should be?
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reproducibility
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responsibility
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creativity
Frage 49
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What is Temporal Locality?
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recently accessed items are likely to be accessed in the near future
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items whose addresses are near one another tend to be referenced close together in time
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the nearest data stored in secondary memory
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What is Spatial Locality?
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items whose addresses are near one another tend to be refer¬enced close together in time
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recently accessed items are likely to be accessed in the near future
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the nearest data stored in secondary memory
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What is Amdahl's law?
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Defines the speedup that can be gained by using a particular feature
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Defines time spent on execution of a program
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Defines data gained in one operation
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The most popular scheme is set associative, where a set is?
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a group of blocks
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a group of instructions
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a group of comparatives
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The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
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The very first access to a block cannot be in the cache, so the block must be brought into the cache
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If the cache cannot contain all the blocks needed during execution of a program
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If the block placement strategy is not fully associative
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The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
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If the cache cannot contain all the blocks needed during execution of a program
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The very first access to a block cannot be in the cache, so the block must be brought into the cache
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If the block placement strategy is not fully associative
Frage 55
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The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
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If the block placement strategy is not fully associative
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The very first access to a block cannot be in the cache, so the block must be brought into the cache
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If the cache cannot contain all the blocks needed during execution of a program
Frage 56
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The “natural” unit of organization of memory
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Word
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Document
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Several Computer
Frage 57
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Main element of cache memory is …
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Typical levels of Cache memories …
Frage 59
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Select internal memory …
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Hard Disk
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CD-ROM
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Processor registers
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Select internal memory
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Hard Disk
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Optical disk
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Main memory
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Select internal memory
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Cache
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Magnetic tape
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Optical disks
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Select external memory?
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Processor registers
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Cache
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Main memory
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Hard disks
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Select external memory
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Optical Disk
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Cache level 1
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Registers of processor
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Select external memory
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Magnetic tape
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Main memory
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All cache memories
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Physical types of memories:
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Direct, Random
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Direct, Access time
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Semiconductor, Optical
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Physical types of memories:
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Semiconductor, Magnetic
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Word, Block
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Direct, Random
Frage 67
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Physical types of memories:
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Magneto-optical
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Number of words
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Number of bytes
Frage 68
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Select correct memory hierarchy:
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Cache – Main Memory – Secondary storages
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Secondary storages - Cache – Main Memory
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Main Memory – Cache - Secondary storages
Frage 69
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Select correct memory hierarchy:
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Processor registers – Cache memory – Main memory
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Cache memory – Main memory - Processor registers
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Cache memory – Processor registers - Main memory
Frage 70
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External, nonvolatile memory is also referred to as …
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auxiliary memory
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Main memory
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Levels of cache
Frage 71
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Types of cache addresses
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Logical, Physical
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Direct, Associative
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Set Associative
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A logical cache stores data using …
Frage 73
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The two basic forms of semiconductor random access memory are
Frage 74
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Main element of cache memory
Frage 75
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A number of chips can be grouped together to form …
Antworten
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a memory bank
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a memory tags
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a memory linis
Frage 76
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Data are recorded on and later retrieved from the disk via a conducting coil named
Antworten
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The arm
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The slid
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The head
Frage 77
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The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
Frage 78
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To increase density, modern hard disk systems use a technique known as
Frage 79
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… can be removed and replaced with another disk.
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Processor registers
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A nonremovable disk
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A removable disk
Frage 80
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For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
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double sided
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single sided
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no sides
Frage 81
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The set of all the tracks in the same relative position on the platter is referred to as …
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a cylinder
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a square
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a circle
Frage 82
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On a movable head system, the time it takes to position the head at the track is known as …
Antworten
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transfer time
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access time
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seek time
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The operating system …
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is the software that controls the execution of programs on a processor and that manages the processor’s resources.
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is one which is understandable by us humans
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is a collection of Clusters/Warehouse-scale computers
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a program that directly executes instructions written in a programming language
Frage 84
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The most important functions of the Operating System are
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The scheduling of processes, or tasks
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Compile C++ program codes
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Interpret PHP program codes
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Provide drivers for the remote devices
Frage 85
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The important function of the Operating System is
Frage 86
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How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
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Program execution
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Access to I/O devices
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Program creation
Frage 87
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How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
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Program creation
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Access to I/O devices
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Program execution
Frage 88
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How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
Antworten
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Access to I/O devices
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Program execution
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Program creation
Frage 89
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How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
Frage 90
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How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
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How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
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Select two independent dimensions of the Operating System
Frage 93
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Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
Frage 94
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Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
Antworten
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Bufferable (B) bit
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Cacheable (C) bit
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Type Extension (TEX)
Frage 95
Antworten
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It indicates how the nodes a network are organized
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It is the delay in transferring the message between two nodes
-
It is the minimum distance between the farthest nodes in a network