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Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:
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a system clock
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a system processor
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a clock processor
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a processor
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a clock
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Typically all operations performed by a processor begin with the:
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The time between pulses called?
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clock speed
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clock rate
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cycle time
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clock cycle
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cycle rate
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Typically, clock signals are generated by a ______, which generates a constant signal wave while power is applied.
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quartz crystal
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calcium crystal
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zinc crystal
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mercury crystal
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radium crystal
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A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:
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Instruction execution rate
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Instruction execution cycle
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Instruction execution time
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Instruction execution period
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None of the above
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Average cycles per instruction of a program called:
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CPU
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Clock cycle time
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CPI
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Clock rate
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CPE
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__ is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.
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A benchmark suite
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A performance suite
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A IDE suite
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A MIPS suite
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None of the above
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Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors
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SPEC Benchmarks, which evaluates the performance of World Wide Web (WWW) servers:
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SPECjvm98
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SPECjbb2000
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SPECweb99
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SPECmail2001
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all of the above
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SPEC Benchmarks, which intended to evaluate performance of the combined hardware and software aspects of the Java Virtual Machine (JVM) client platform:
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SPECjvm98
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SPECjbb2000
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SPECweb99
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SPECmail2001
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all of the above
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SPEC Benchmarks, which for evaluating server-side Java-based electronic commerce applications:
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SPECjvm98
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SPECjbb2000
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SPECweb99
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SPECmail2001
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all of the above
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SPEC Benchmarks, which designed to measure a system’s performance acting as a mail server
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SPECjvm98
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SPECjbb2000
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SPECweb99
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SPECmail2001
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all of the above
Frage 13
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Electronic Numerical Integrator and Computer
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Electronic Nuclear Integrator and Computer
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Encapsulation Numerical Integrator and Commerce
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Encapsulation Numerical Integrator and Computer
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Electronic Numerical Integer and Computer
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The general structure of the IAS computer:
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Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
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Memory buffer register (MBR)
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Memory address register (MAR)
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Instruction register (IR)
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Instruction buffer register (IBR)
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Program counter (PC)
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Specifies the address in memory of the word to be written from or read into the MBR
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Memory buffer register (MBR)
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Memory address register (MAR)
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Instruction register (IR)
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Instruction buffer register (IBR)
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Program counter (PC)
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Contains the 8-bit opcode instruction being executed.
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Memory buffer register (MBR)
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Memory address register (MAR)
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Instruction register (IR)
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Instruction buffer register (IBR)
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Program counter (PC)
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Employed to hold temporarily the right-hand instruction from a word in memory
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Memory buffer register (MBR)
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Memory address register (MAR)
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Instruction register (IR)
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Instruction buffer register (IBR)
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Program counter (PC)
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Contains the address of the next instruction pair to be fetched from memory.
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Memory buffer register (MBR)
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Memory address register (MAR)
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Instruction register (IR)
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Instruction buffer register (IBR)
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Program counter (PC)
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Transistor is a solid-state device, made from silicon
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The use of the _______ defines the second generation of computers.
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The use of the _______ defines the first generation of computers.
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The use of the ________ defines the third generation of computers.
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The use of the _________ defines the fourth generation of computers.
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The use of the _________ defines the fifth generation of computers.
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Moore’s law: “The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic
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Moore’s law: “Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed”
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Moore’s law: “The computer becomes smaller, making it more convenient to place in a variety of environments”
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Moore’s law: “There is a reduction in power and cooling requirements”
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Moore’s law: “The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections”
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When Intel was developed its 4004, it is the first chip to contain all of the components of a CPU on a single chip, later known as Microprocessor
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Processor can simultaneously work on multiple instructions. How this technique called?
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Branch prediction
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Pipelining
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Data flow analysis
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Speculative execution
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None of the above
Frage 33
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The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next
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Branch prediction
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Pipelining
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Data flow analysis
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Speculative execution
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None of the above
Frage 34
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The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
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Branch prediction
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Pipelining
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Data flow analysis
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Speculative execution
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None of the above
Frage 35
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This enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed
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Branch prediction
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Pipelining
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Data flow analysis
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None of the above
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Speculative execution
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The “natural” unit of organization of memory
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Word
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Addressable units
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Unit of transfer
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Sequential access
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Direct access
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For main memory, this is the number of bits read out of or written into memory at a time
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Word
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Addressable units
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Unit of transfer
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Sequential access
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Direct access
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Memory is organized into units of data, called records; access must be made in a specific linear sequence
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Word
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Addressable units
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Unit of transfer
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Sequential access
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Direct access
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For random-access memory, this is the time it takes to perform a read or write operation
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Access time
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Memory cycle time
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Transfer rate
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Performance
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All of the above
Frage 40
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The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
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The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
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Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches
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Each cache controller monitors the address lines to detect write operations to memory by other bus masters
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Only a portion of main memory is shared by more than one processor, and this is designated as:
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Larger blocks increase the number of blocks that fit into a cache; because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched
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A state in which data requested for processing by a component or application is found in the cache memory
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cache hit
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cache miss
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cache overwrites
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cache set
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cache access time
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The basic element of a semiconductor memory is:
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memory cell
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cache memory
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RAM
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DRAM
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None of the above
Frage 48
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Random Access Integral Disk
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Redundant Access Integral Disk
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Random Array Independent Disk
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Redundant Array Independent Disk
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Redundant Access Independent Disk
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Data are recorded on and later retrieved from the disk via a conducting coil named the tail