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The figure below illustrates a partial program execution
What is the address of the instruction that is being executed?
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What is NOT a main structural element of a computer system?
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System bus
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Main memory
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Operating system
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Processor
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Which of the following element of a computer system controls the operation of the computer and performs its data processing functions?
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Main Memory
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I/O modules
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Processor
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System bus
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This register specifies the location in memory for the next read or write
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I/OAR
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I/OBR
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Memory Address Register
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Memory Buffer Register
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Complete the relationship concerning the memory systems: faster access time —
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slower access speed
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greater capacity
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smaller cost per bit
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greater cost per bit
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When a processor attempts to read a byte or word of memory, it firstly checks the:
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Cache
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Disk
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CD
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Main memory
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Complete the relationship concerning the memory systems: greater capacity —
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faster access speed
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greater cost per bit
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smaller cost per bit
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lower capacity
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The processor contains a single data register, called:
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As one goes down the memory hierarchy
the following occurs
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The figure below shows:
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Parent-child interrupt processing
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Nested interrupt processing
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Parallel interrupt processing
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Sequential interrupt processing
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The figure below shows:
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Nested interrupt processing
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Parallel interrupt processing
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Parent-child interrupt processing
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Sequential interrupt processing
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At the beginning of each instruction cycle, the processor fetches an instruction from the memory. The address of the instruction is held in:
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Which of the following registers are used by the processor to exchange data with input/output module?
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MAR and MBR
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PC and IR
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I/OAR and I/OBR
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Program status word
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Which of the following element of a computer system moves data between the computer and its external environment?
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I/O modules
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Processor
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Main memory
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System bus
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Which register contains the address of the next instruction to be fetched?
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Instruction register
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Program counter
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Execution register
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Process counter
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Which register contains the instruction most recently fetched?
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Program counter
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Process counter
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Execution register
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Instruction register
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Choose the micro-instructions that reflect instruction execution stage shown in the figure below:
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IR → MAR 941
M → MBR 0002
MBR → AC 0002
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PC → MAR 303
M → MBR 2941
MBR → IR 2941
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PC → MAR 302
M → MBR 2941
MBR → IR 2941
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IR → MAR 941
M → MBR 0005
MBR → AC 0005
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Choose the micro-instructions that reflect instruction execution stage shown in the figure below:
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IR → MAR 941
M → MBR 0002
MBR → AC 0005
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IR → MAR 941
M → MBR 0002
MBR → AC 0002
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PC → MAR 302
M → MBR 2941
MBR → IR 2941
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PC → MAR 301
M → I/OBR 5941
I/OBR → IR 5941
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Choose the micro-instructions that reflect instruction execution stage shown in the figure below:
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PC → MAR 300
M → MBR 1940
MBR → IR 1940
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M → MAR 300
M → MBR 1940
MBR → IR 1940
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PC → MAR 300
M → MAR 1940
MBR → IR 1940
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PC → MAR 301
M → MBR 1940
MBR → IR 1940
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Choose the micro-instructions that reflect execution stage shown in the figure below:
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IR → MAR 1940
M → MBR 0003
MBR → AC 0003
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PC → MAR 300
M → MBR 1940
MBR → IR 1940
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IR → MAR 940
M → MBR 940
MBR → AC 0003
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IR → MAR 940
M → MBR 0003
MBR → AC 0003
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The figure below illustrates a partial program execution
What is the memory location of the data that is addressed in the instruction?
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The figure below illustrates a partial program execution.
What is the memory location of the data that is addressed in the instruction?
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The figure below illustrates a partial program execution
Instruction in the IR will:
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Add 2 to AC from the memory
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Store 3 to AC from the memory
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Load 3 to AC from the memory
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Add 3 to AC from the memory
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When an I/O device completes an I/O operation, the device issues an interrupt signal to the processor and then:
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The processor finishes the execution of the current instruction before responding to the interrupt
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The processor loads the program counter with the entry location of the interrupt-handling routine
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The processor saves information needed to resume the current program at the point if interrupt
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The processor stops execution of the current instruction without finishing it and responds to the interrupt
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The figure a) demonstrates the program timing diagram for:
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Interrupts; slow I/O wait
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Interrupts; long I/O wait
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Interrupts; short I/O wait
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Interrupts; fast I/O wait
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No interrupts
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The smaller, more expensive, faster memory is:
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Main memory
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Register
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Cache
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Disk drive
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If the contents of a block in the cache are altered, then it is needed to save it back to main memory before replacing it. This is called:
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mapping function
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replacement algorithm
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write policy
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locality of reference
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Complete the relationship concerning the memory systems: greater capacity —
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lower capacity
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slower access speed
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faster access speed
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greater cost per bit
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We have
Ts = average (system) access time
T1 = access time of M1 (e.g. cache)
T2 = access time of M2 (e.g. main memory)
T3 = access time of M3 (e.g. disk)
H1 = hit ratio, fraction of time reference is found in M1
H2 = hit ratio, fraction of time reference is found in M2
The average time to access an item in case the item in cache is:
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Which register contains condition codes set by the processor hardware as the result of operations?
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Accumulator
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Program counter
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Stack pointer
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Program status word
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If the accessed word is not found in the faster memory, that is defined as a:
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Which of the following element of a computer system stores data and programs?
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Main memory
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Processor
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System bus
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I/O modules
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The processor is executing 'Load AC from memory' instruction. Choose the correct micro-instructions:
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PC → MAR M → MBR MBR → IR IR → MAR M → MBR MBR → AC
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PC → MAR M → MBR MBR → IR IR → MBR M → MAR MAR → AC
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PC → MAR M → MBR MBR → AC IR → MAR M → MBR MBR → AC
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PC → MBR M → MAR MAR → IR IR → MAR M → MBR MBR → AC
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The processor determined that there is a pending interrupt and sent an acknowledgement signal to the device that issued the interrupt. Then, the processor:
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Pause and remain idle until the I/O operation finishes
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Saves the current state of the program being executed
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Fetches new instruction from the user program and executes it
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Loads new PC value based on interrupt
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As one goes down the memory hierarchy
the following occurs:
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When the time required for the I/O operation is less than the time to complete the execution of instructions between write operations in the user program, it is:
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Fast I/O wait
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Short I/O wait
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Slow I/O wait
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Long I/O wait
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We have
Ts = average (system) access time
T1 = access time of M1 (e.g. cache)
T2 = access time of M2 (e.g. main memory)
T3 = access time of M3 (e.g. disk)
H1 = hit ratio, fraction of time reference is found in M1
H2 = hit ratio, fraction of time reference is found in M2
The average time to access an item in case the item in cache is:
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Ts = H1 × T1 + H2 × T2 + (1 — H2) × T3
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Ts = H1 × H1 + (1 — H1) × (H2 × (T1 + T2) + (1 — H2) × (T1 + T2 + T3))
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Ts = H1 × H1 + (1 — H1) × (H2 × (T2 + T3)
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Ts = H1 × H1 + (1 — H1) × (H1 × T1 + H2 × (T1+T2) + (1 — H2) × (T2 + T3))
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The type of memory is nonvolatile:
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Secondary memory
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Cache
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Main memory
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Register
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Which of the following provides for communication among elements of a computer system?
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I/O modules
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Processor
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Main memory
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System bus