CSA Last p2

Question

Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?

Answer 1

Integer Datapath

Answer 2

Address Queue

Answer 3

Very Long Instruction Word

Answer 4

Very Less Interpreter Word

Answer 5

Very Light Internal Word

Answer 6

Very Low Invalid Word

Answer 7

Loop Unrolled

Answer 8

Software Pipelined

Answer 9

Software Pipelined

Answer 10

Loop Unrolled

Answer 11

Speculative operations that don’t cause exceptions

Answer 12

Hardware to check pointer hazards

Answer 13

Hardware to check pointer hazards

Answer 14

Speculative operations that don’t cause exceptions

Answer 15

Advanced Load Address Table

Answer 16

Allocated Link Address Table

Answer 17

Allowing List Address Table

Answer 18

Addition Long Accessibility Table

Answer 19

Allow one instruction to branch multiple directions

Answer 20

Speculative operations that don’t cause exceptions

Answer 21

first-reference to a block, occur even with infinite cache

Answer 22

cache is too small to hold all data needed by program, occur even under perfect replacement policy

Answer 23

misses that occur because of collisions due to less than full associativity

Answer 24

cache is too small to hold all data needed by program, occur even under perfect replacement policy

Answer 25

first-reference to a block, occur even with infinite cache

Answer 26

misses that occur because of collisions due to less than full associativity

Answer 27

process that applies binary logic to yield binary results

Answer 28

to determine whether an IP address exists on the local network or whether it must be routed outside the local network.

Answer 29

It sends out ICMP (Internet Control Message Protocol) messages to verify both the logical addresses & the Physical connection.

Answer 30

to determine whether an IP address exists on the global network or whether it must be routed outside the global network.

Answer 31

Lancaster University

Answer 32

Manchester University

Answer 33

Better performance: we can use more memory than we have

Answer 34

Nothing; mapping to memory or disk is just as easy

Answer 35

Worse performance: reading from disk is slower than RAM

Answer 36

Good performance: reading from disk is slower than RAM

Answer 37

Not enough memory

Answer 38

Holes in the address space

Answer 39

Keeping program secure

Answer 40

Keeping program insecure

Answer 41

process refers to the logical (or virtual) view of how a process is stored in memory

Answer 42

used to translate the virtual addresses seen by the application into physical addresses

Answer 43

a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.

Answer 44

none of the mentioned

Answer 45

process refers to the logical (or virtual) view of how a process is stored in memory

Answer 46

used to translate the virtual addresses seen by the application into physical addresses

Answer 47

a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.

Answer 48

none of the mentioned

Answer 49

Cache Memory

Answer 50

parallel; systems

Answer 51

tightly coupled system

Answer 52

loosely coupled system

Answer 53

both a and b

Answer 54

Combinational circuits has memory

Answer 55

Sequential circuits has memory

Answer 56

Sequential circuits is a function of time

Answer 57

Combinational circuits does not require feedback paths

Answer 58

Sequential circuits require feedback paths.

Answer 59

Von-Neumann

Answer 60

Transistors

Answer 61

Vacuum Tubes

Answer 62

Binary-Adder

Answer 63

Full-Adder

Answer 64

Half-Adder

Answer 65

Accumulator

Answer 66

Shift Register

Answer 67

Control Unit

Answer 68

Dynamic RAM

Answer 69

Static RAM

Answer 70

Main memory

Answer 71

Cache memory

Answer 72

Auxiliary memory

Answer 73

Quadrillion

Answer 74

MIPS and ARM

Answer 75

Pentium 4, MIPS R12K, IBM, Power5

Answer 76

None at the present

Answer 77

Pentium 4, MIPS R12K, IBM, Power5

Answer 78

MIPS and ARM

Answer 79

Execution in the OS that is neither idle nor in synchronization access

Answer 80

Execution in user code

Answer 81

Execution or waiting for synchronization variables

Answer 82

Execution or waiting for synchronization variables

Answer 83

Execution in the OS that is neither idle nor in synchronization access

Answer 84

Execution in user code

Answer 85

Sequential circuit is an interconnection of only logic gates

Answer 86

Sequential circuit is an interconnection of only flip flops

Answer 87

Combinational circuit is an interconnection of logic gates

Answer 88

Combinational circuit is an interconnection of flip flops

Answer 89

Part of a combinational circuit is a sequential circuit.

Answer 90

Reduced Instruction Sign Computers

Answer 91

Reduced Instruction Set Computers

Answer 92

Reduced Instruction Set Carry

Answer 93

Reduced Invalid Set Computers

Answer 94

Reset Instruction Set Computers.

Answer 95

branch folding

Answer 96

Branch prediction

Answer 97

Target instructions

Answer 98

Target address

Answer 99

Instruction memory commit

Answer 100

Integrated branch prediction

Answer 101

Instruction prefetch

Answer 102

Instruction memory access and buffering

Answer 103

Address aliasing prediction

Answer 104

Branch prediction

Answer 105

Integrated branch prediction

Answer 106

Dynamic branch prediction

Answer 107

Reduced Instruction Set Computer

Answer 108

Recall Instruction Sell Communication

Answer 109

Rename Instruction Sequence Corporation

Answer 110

Red Instruction Small Computer

Answer 111

the maximum performance attainable by the implementation

Answer 112

the maximum performance attainable by the instruction

Answer 113

the minimum performance attainable by the implementation

Answer 114

the minimum performance attainable by the instruction

Answer 115

Ideal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls

Answer 116

Ideal pipeline CPU + Data hazard stalls + Control stalls

Answer 117

Ideal pipeline CPU + Ideal pipeline CPI + Data hazard stalls + Control stalls

Answer 118

Structural stalls + Data hazard stalls + Control stalls

Answer 119

to exploit parallelism among iterations of a loop

Answer 120

to exploit minimalism among iterations of a loop

Answer 121

to destroy iterations of a loop

Answer 122

to decrease the minimalism of risk

Answer 123

loop-level parallelism

Answer 124

exploit-level parallelism

Answer 125

high-level minimalism

Answer 126

low-level minimalism

Answer 127

data dependences, name dependences and control dependences

Answer 128

data dependences, name dependences, and surname dependences

Answer 129

datagram dependences ,name dependences, and animal dependences

Answer 130

no correct answers

Answer 131

name dependence occurs when two instructions use the same register or memory location

Answer 132

name dependence occurs when five or more instructions use the same register or memory location

Answer 133

name dependence occurs when instructions use the same name

Answer 134

All answers is correct

Answer 135

When i and instruction j write the same register or memory location

Answer 136

when i and instruction j write the same name

Answer 137

when i and instruction j write the same address or memory location

Answer 138

All answers is correct

Answer 139

when j tries to read a source before i writes it, so j incorrectly gets the old value

Answer 140

when i tries to read a source before j writes it, so j correctly gets the old value

Answer 141

when j tries to write a source before i writes it

Answer 142

when a tries to write a source before b read it, so a incorrectly gets the old value

Answer 143

loop unrolling

Answer 144

loop-level

Answer 145

loop rolling

Answer 146

register pressure

Answer 147

loop unrolling

Answer 148

loop-level

Answer 149

registration

Answer 150

branch-prediction buffer

Answer 151

branch buffer

Answer 152

All answers correct

Answer 153

registration

Answer 154

correlating predictors or two-level predictors

Answer 155

branch-prediction buffer

Answer 156

branch table

Answer 157

three level loop

Answer 158

The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.

Answer 159

If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 160

The number of accesses that miss divided by the number of accesses.

Answer 161

None of them

Answer 162

If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 163

The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.

Answer 164

The number of accesses that miss divided by the number of accesses.

Answer 165

None of them

Answer 166

If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set

Answer 167

The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.

Answer 168

If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 169

None of them

Answer 170

Larger block size to reduce miss rate

Answer 171

Bigger caches to increase miss rat

Answer 172

Single level caches to reduce miss penalty

Answer 173

None of them

Answer 174

Critical word first

Answer 175

Critical restart

Answer 176

Sequential inter leaving

Answer 177

Merging Write Buffer to Reduce Miss Penalty

Answer 178

Merging Write Buffer to Reduce Miss Penalty

Answer 179

Critical word first

Answer 180

Nonblocking Caches to Increase Cache Bandwidth

Answer 181

Trace Caches to Reduce Hit Time

Answer 182

Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate

Answer 183

Merging Write Buffer to Reduce Miss Penalty

Answer 184

Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate

Answer 185

None of them

Answer 186

Time between when a read is requested and when the desired word arrives

Answer 187

The minimum time between requests to memory.

Answer 188

Describes the technology inside the memory chips and those innovative, internal organizations

Answer 189

None of them

Answer 190

The minimum time between requests to memory.

Answer 191

Time between when a read is requested and when the desired word arrives

Answer 192

The maximum time between requests to memory.

Answer 193

None of them

Answer 194

Dynamic Random Access memory

Answer 195

Dual Random Access memory

Answer 196

Dataram Random Access memory

Answer 197

Double data rate

Answer 198

Dual data rate

Answer 199

Double data reaction

Answer 200

None of them

Answer 201

Microprocessor

Answer 202

Main memory

Answer 203

Storage device

Answer 204

Data of the current instruction

Answer 205

Next Instruction which is to be executed

Answer 206

Address of the current instruction

Answer 207

Instruction which is currently executed

Answer 208

Address space

Answer 209

Disk space

Answer 210

Memory space

Answer 211

Selective Clear

Answer 212

Selective Complement

Answer 213

Selective Set

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CSA Last p2

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