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PCA_Final_Exam_New_Questions

Question 1 of 184

1

In 32-bit addressing mode, address field is either 1 byte or?

Select one of the following:

  • 4 bytes

  • 2 bytes

  • 6 bytes

Explanation

Question 2 of 184

1

If a block can be placed at every location in cache, this cache is said to be?

Select one of the following:

  • Fully associative

  • Directly mapped

  • Indirectly mapped

Explanation

Question 3 of 184

1

Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?

Select one of the following:

  • Write-through

  • Write-back

  • Miss rate

Explanation

Question 4 of 184

1

Average access time of memory for having memory-hierarchy performance is given as?

Select one of the following:

  • Average memory access time = Hit time - Miss rate

  • Average memory access time = Hit time + (miss rate and miss penalty)

  • Average memory access time = Hit time + Miss rate - Miss penalty

Explanation

Question 5 of 184

1

As segment or a page is normally used for block, page-fault and address-fault is used for:

Select one of the following:

  • Hit

  • Miss

  • Cache

  • Stack

Explanation

Question 6 of 184

1

Virtual memory producing virtual-addresses, are translated by:

Select one of the following:

  • Logical addresses

  • Physical addresses

  • Local addresses

  • All above

Explanation

Question 7 of 184

1

Per memory reference, miss-rate can be turned into per instruction misses rate by

Select one of the following:

  • Miss rate= Memory accesses* instructions

  • Miss rate= Memory accesses/ instructions

  • Miss rate= Memory accesses-instructions

  • Miss rate= Memory accesses+ instructions

Explanation

Question 8 of 184

1

Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as

Select one of the following:

  • Read back

  • Cache miss

  • Virtual memory

  • Cache hit

Explanation

Question 9 of 184

1

For reducing frequency on replacement of write-back blocks, commonly used feature, is known as:

Select one of the following:

  • Hit miss

  • Index field

  • Dirty bit

  • Write-through

Explanation

Question 10 of 184

1

If cache is not able for containing all blocks needed while execution, miss is then known as

Select one of the following:

  • Hit miss

  • Cache hit

  • Cache miss (capacity miss)

  • Hit rate

Explanation

Question 11 of 184

1

For completing programmer's desire for unlimited quick memory, suggested economical solution was:

Select one of the following:

  • Memory hierarchy

  • Temporal locality

  • Spatial locality

Explanation

Question 12 of 184

1

An instruction that does no operation for changing state is known as

Select one of the following:

  • Nope

  • No

  • NOP

Explanation

Question 13 of 184

1

Set of instructions examined as candidates for potential execution is called the

Select one of the following:

  • Frame

  • Cube

  • Window

Explanation

Question 14 of 184

1

Term 'computer architecture' is sometimes referred only to:

Select one of the following:

  • Instruction set design

  • Circuit design

  • Hardware design

Explanation

Question 15 of 184

1

General categories of instructions' operation are

Select one of the following:

  • Data transfer

  • Arithmetic logical

  • floating point

  • All above

Explanation

Question 16 of 184

1

The effectiveness of the cache memory is based on the property of:

Select one of the following:

  • Locality of reference

  • Memory localization

  • Memory size

Explanation

Question 17 of 184

1

The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.

Select one of the following:

  • Level 2 cache

  • Level 1 cache

  • Registers

Explanation

Question 18 of 184

1

The last on the hierarchy scale of memory devices is ______.

Select one of the following:

  • Main memory

  • Branch

  • Secondary memory

Explanation

Question 19 of 184

1

A common measure of performance is

Select one of the following:

  • Price/performance ratio.

  • Performance/price ratio

  • Operation/price ratio.

Explanation

Question 20 of 184

1

The number successful accesses to memory stated as a fraction is called as _____

Select one of the following:

  • Miss rate

  • Hit rate

  • Access rate

Explanation

Question 21 of 184

1

With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as:

Select one of the following:

  • Scalability

  • Module availability

  • Module reliability

Explanation

Question 22 of 184

1

From a reference initial instant, a measure of service accomplishment, is known as:

Select one of the following:

  • Module reliability

  • Hardware

  • Sector

Explanation

Question 23 of 184

1

To initialize any port as an output port what value is to be given to it?

Select one of the following:

  • 0xFF

  • 0x00

  • 0x01

  • A port is by default an output port

Explanation

Question 24 of 184

1

In AVR, which registers are there for the I/O programming of ports?

Select one of the following:

  • all above

  • PORT

  • PIN

  • DDR

Explanation

Question 25 of 184

1

The data will not go from the port registers to the pin unless:

Select one of the following:

  • DDR register of that port is set to 0

  • DDR register of that port is set to 1

  • PORT register of that port is set to 0

Explanation

Question 26 of 184

1

What is the file extension that is loaded in a micro controller for executing any instruction?

Select one of the following:

  • .doc

  • .hex

  • .txt

Explanation

Question 27 of 184

1

What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?

Select one of the following:

  • True sharing misses

  • False sharing misses

Explanation

Question 28 of 184

1

What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:

Select one of the following:

  • False sharing misses

  • True sharing misses

Explanation

Question 29 of 184

1

At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?

Select one of the following:

  • One or more processors have the block cached, and the value in memory is up to date

  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date

  • No processor has a copy of the cache block

Explanation

Question 30 of 184

1

At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?

Select one of the following:

  • No processor has a copy of the cache block

  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date

  • One or more processors have the block cached, and the value in memory is up to date

Explanation

Question 31 of 184

1

At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Uncached” in a simple protocol?

Select one of the following:

  • No processor has a copy of the cache block

  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date

  • One or more processors have the block cached, and the value in memory is up to date

Explanation

Question 32 of 184

1

In Non-Blocking Caches what does mean “Early restart”?

Select one of the following:

  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Explanation

Question 33 of 184

1

What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?

Select one of the following:

  • n loop iterations

  • subroutine call

  • vector access

Explanation

Question 34 of 184

1

What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?

Select one of the following:

  • subroutine call

  • n loop iterations

  • vector access

Explanation

Question 35 of 184

1

What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?

Select one of the following:

  • subroutine call

  • n loop iterations

  • vector access

Explanation

Question 36 of 184

1

What is kernel process?

Select one of the following:

  • Provide at least two modes, indicating whether the running process is a user process or an operating system process

  • Provide at least five modes, indicating whether the running process is a user process or an operating system process

  • Provide a portion of the processor state that a user process can use but not write

  • None of them

Explanation

Question 37 of 184

1

Which one is NOT concerning to pitfall?

Select one of the following:

  • Predicting cache performance of one program from another

  • Simulating enough instructions to get accurate performance measures of the memory hierarchy

  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

  • Over emphasizing memory bandwidth in DRAMs

Explanation

Question 38 of 184

1

Which one is concerning to fallacy?

Select one of the following:

  • Predicting cache performance of one program from another

  • Simulating enough instructions to get accurate performance measures of the memory hierarchy

  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

  • Over emphasizing memory bandwidth in DRAMs

Explanation

Question 39 of 184

1

At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?

Select one of the following:

  • Speculative operations that don’t cause exceptions

  • Hardware to check pointer hazards

Explanation

Question 40 of 184

1

At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:

Select one of the following:

  • Hardware to check pointer hazards

  • Speculative operations that don’t cause exceptions

Explanation

Question 41 of 184

1

At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:

Select one of the following:

  • Allow one instruction to branch multiple directions

  • Speculative operations that don’t cause exceptions

Explanation

Question 42 of 184

1

In Multilevel Caches “Local miss rate” equals =

Select one of the following:

  • misses in cache / accesses to cache

  • misses in cache / CPU memory accesses

  • misses in cache / number of instructions

Explanation

Question 43 of 184

1

In Multilevel Caches “Global miss rate” equals =

Select one of the following:

  • misses in cache / CPU memory accesses

  • misses in cache / accesses to cache

  • misses in cache / number of instructions

Explanation

Question 44 of 184

1

In Multilevel Caches “Misses per instruction” equals =

Select one of the following:

  • misses in cache / number of instructions

  • misses in cache / accesses to cache

  • misses in cache / CPU memory accesses

Explanation

Question 45 of 184

1

The time between the start and the completion of an event ,such as milliseconds for a disk access is...

Select one of the following:

  • latency

  • bandwidth

  • throughput

  • performance

Explanation

Question 46 of 184

1

Total amount of work done in a given time , such as megabytes per second for disk transfer...

Select one of the following:

  • bandwidth (throughput)

  • latency

  • performance

Explanation

Question 47 of 184

1

Products that are sold by multiple vendors in large volumes and are essentially identical

Select one of the following:

  • commodities

  • boxes

  • folders

  • files

Explanation

Question 48 of 184

1

Integrated circuit processes are characterized by the:

Select one of the following:

  • feature size

  • permanent size n

  • complex size

  • fixed size

Explanation

Question 49 of 184

1

Manufacturing costs that decrease over time are ____

Select one of the following:

  • the learning curve

  • the cycled line

  • the regular option

  • the final loop

Explanation

Question 50 of 184

1

Volume is a ________ key factor in determining cost.

Select one of the following:

  • second

  • first

  • fifth

  • third

Explanation

Question 51 of 184

1

The most companies spend only ____________ of their income on R&D, which includes all engineering.

Select one of the following:

  • 4% to 12%

  • 15% to 30%

  • 1% to 17%

  • 30% to 48%

Explanation

Question 52 of 184

1

Desktop benchmarks divide into __ broad classes:

Select one of the following:

  • two

  • three

  • four

  • five

Explanation

Question 53 of 184

1

A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.

Select one of the following:

  • 90% 10%

  • 50% 50%

  • 70% 30%

  • 89% 11%

Explanation

Question 54 of 184

1

(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:

Select one of the following:

  • Speedup

  • Efficiency

  • Probability

  • Ration

Explanation

Question 55 of 184

1

Which of the following descriptions corresponds to static power?

Select one of the following:

  • Grows proportionally to the transistor count (whether or not the transistors are switching)

  • Proportional to the product of the number of switching transistors and the switching rate Probability

  • Proportional to the product of the number of switching transistors and the switching rate

  • All of the above

Explanation

Question 56 of 184

1

If we want to sustain four instructions per clock

Select one of the following:

  • We must fetch more, issue more, and initiate execution on more than four instructions

  • We must fetch less, issue more, and initiate execution on more than two instructions

  • We must fetch more, issue less, and initiate execution on more than three instructions

  • We must fetch more, issue more, and initiate execution on less than five instructions

Explanation

Question 57 of 184

1

What is a hash table?

Select one of the following:

  • Popular data structure for organizing a large collection of data items so that one can quickly answer questions

  • Popular data structure for updating large collections, so that one can hardly answer questions

  • Popular tables for organizing a large collection of data structure

  • Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Explanation

Question 58 of 184

1

How this process called: “Operations execute as soon as their operands are available”

Select one of the following:

  • data flow execution

  • instruction execution

  • data control execution

  • instruction field execution

Explanation

Question 59 of 184

1

For what the reorder buffer is used :

Select one of the following:

  • To pass results among instructions that may be speculated.

  • To pass parameters through instructions that may be speculated

  • To get additional registers in the same way as the reservation stations

  • To control registers

Explanation

Question 60 of 184

1

Which one is not the major flavor of Multiple-issue processors:

Select one of the following:

  • statistically superscalar processors

  • dynamically scheduled superscalar processors

  • statically scheduled superscalar processors

  • VLIW (very long instruction word) processors

Explanation

Question 61 of 184

1

Examples of superscalar(static):

Select one of the following:

  • MIPS and ARM

  • Pentium 4, MIPS R12K, IBM, Power5

  • Itanium

  • TI C6x

Explanation

Question 62 of 184

1

Examples of superscalar(dynamic) :

Select one of the following:

  • None at the present

  • Pentium 4, MIPS R12K, IBM, Power5

  • MIPS and ARM

  • TI C6x

Explanation

Question 63 of 184

1

Examples of VLIW processor:

Select one of the following:

  • TI C6x

  • MIPS and ARM

  • Itanium

  • Pentium 4, MIPS R12K, IBM, Power5

Explanation

Question 64 of 184

1

Which is not the function of integrated instruction fetch unit:

Select one of the following:

  • Instruction memory commit

  • Integrated branch prediction

  • Instruction prefetch

  • Instruction memory access and buffering

Explanation

Question 65 of 184

1

In the memory hierarchy, as the speed of operation increases the memory size also increases:

Select one of the following:

  • True
  • False

Explanation

Question 66 of 184

1

At VLIW by “performance and loop iteration” which time is longer?

Select one of the following:

  • Loop Unrolled

  • Software Pipelined

Explanation

Question 67 of 184

1

At VLIW by “performance and loop iteration” which time is shorter?

Select one of the following:

  • Software Pipelined

  • Loop Unrolled

Explanation

Question 68 of 184

1

What is a topology in interconnection networks?

Select one of the following:

  • It indicates how the nodes a network are organised

  • It is the minimum distance between the farthest nodes in a network

  • Number of edges connected with a node is called node degree

Explanation

Question 69 of 184

1

What is a Network Diameter?

Select one of the following:

  • It is the minimum distance between the farthest nodes in a network

  • It indicates how the nodes a network are organized

  • Number of edges connected with a node is called node degree

Explanation

Question 70 of 184

1

What is a Node degree?

Select one of the following:

  • Number of edges connected with a node

  • It indicates how the nodes a network are organized

  • It is the minimum distance between the farthest nodes in a network

Explanation

Question 71 of 184

1

What is a Bisection Bandwidth?

Select one of the following:

  • Number of edges required to be cut to divide a network into two halves

  • It indicates how the nodes a network are organized

  • It is the minimum distance between the farthest nodes in a network

Explanation

Question 72 of 184

1

What is Latency?

Select one of the following:

  • It indicates how the nodes a network are organized

  • It is the delay in transferring the message between two nodes

  • It is the minimum distance between the farthest nodes in a network

Explanation

Question 73 of 184

1

What is a Hardware Cost?

Select one of the following:

  • It indicates how the nodes a network are organized

  • The data routing functions are the functions which when executed established the path between the source and the destination

  • It refers to the cost involved in the implementation of an interconnection network

  • It is an indicative measure of the message carrying capacity of a network

Explanation

Question 74 of 184

1

What is a Blocking and Non-Blocking network?

Select one of the following:

  • It indicates how the nodes a network are organized

  • The data routing functions are the functions which when executed establishe the path between the source and the destination

  • In non-blocking networks the route from any free input node to any free output node can always be provided

  • It is an indicative measure of the message carrying capacity of a network

Explanation

Question 75 of 184

1

Design issue of interconnection network

Select one of the following:

  • Software Cost

  • Hardware Cost

  • RLP

  • Symmetry of the network

Explanation

Question 76 of 184

1

What is a Data transfer time?

Select one of the following:

  • It indicates how the nodes a network are organized

  • The data routing functions are the functions which when executed established the path between the source and the destination

  • How long does it take for a message to reach to another processor

  • It is an indicative measure of the message carrying capacity of a network

Explanation

Question 77 of 184

1

Select non-blocking interconnection network

Select one of the following:

  • Linear Array

  • Cube

  • CrossBar

Explanation

Question 78 of 184

1

A modified version of the tree interconnection network

Select one of the following:

  • Fat tree

  • Cube

  • Linear Array

Explanation

Question 79 of 184

1

An interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data

Select one of the following:

  • Systolic Array

  • Cube

  • Linear Array

Explanation

Question 80 of 184

1

A _____________ interconnection network is an extension of cube network

Select one of the following:

  • Hyper Cube

  • Cube

  • Linear Array

Explanation

Question 81 of 184

1

In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.

Select one of the following:

  • Multithreading

  • Computing

  • Array processing

Explanation

Question 82 of 184

1

Single Instruction, Single Data (SISD):

Select one of the following:

  • Only one instruction stream is being acted on by the CPU during any one clock cycle

  • A type of parallel computer

  • Currently, the most common type of parallel computer - most modern supercomputers fall into this category

Explanation

Question 83 of 184

1

Pipelining …

Select one of the following:

  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line

  • A logically discrete section of computational work

  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory

Explanation

Question 84 of 184

1

Shared Memory…

Select one of the following:

  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory

  • A logically discrete section of computational work

  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line

Explanation

Question 85 of 184

1

What is a RISC computers?

Select one of the following:

  • Reduced Instruction Set Computer

  • Rational Interruptible Security Computer

  • Research Interconnect Several Computer

Explanation

Question 86 of 184

1

When single-processor performance improvement has dropped?

Select one of the following:

  • 2003

  • 2004

  • 2002

Explanation

Question 87 of 184

1

How much in percentage single-processor performance improvement has dropped to less than?

Select one of the following:

  • 22%

  • 11%

  • 33%

Explanation

Question 88 of 184

1

How many classes of computers classified?

Select one of the following:

  • 3

  • 5

  • 7

Explanation

Question 89 of 184

1

What is the PMD in computer classes?

Select one of the following:

  • Percentage map device

  • Powerful markup distance

  • Peak maze development

  • Personal mobile device

Explanation

Question 90 of 184

1

What is the Thread Level Parallelism?

Select one of the following:

  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Explanation

Question 91 of 184

1

What is the Request Level Parallelism:

Select one of the following:

  • o Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Explanation

Question 92 of 184

1

What is the Instruction Level Parallelism:

Select one of the following:

  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution

  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Explanation

Question 93 of 184

1

What is the MISD one of the categories of computers?

Select one of the following:

  • Multiple Instructions Streams, Single Data Stream

  • Multiple Instruction Streams, Multiple Data Streams

  • Multiple Instruction Streams, Set Data Stream

Explanation

Question 94 of 184

1

How many elements in Trends of Technology?

Select one of the following:

  • 5

  • 4

  • 6

Explanation

Question 95 of 184

1

How many elements of the Instruction Set Architecture (ISA):

Select one of the following:

  • 7

  • 8

Explanation

Question 96 of 184

1

How many types of dependencies do you know?

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 97 of 184

1

How many possible Elements of Data Hazards?

Select one of the following:

  • 3

  • 6

  • 8

Explanation

Question 98 of 184

1

What is the “ISSUE” in Pipelining Basics?

Select one of the following:

  • Decode instructions, check for structural hazard

  • Decode instructions, check for data hazard

  • Decode instructions, check for control hazard

Explanation

Question 99 of 184

1

What is the “Read Operands” in Pipelining Basics?

Select one of the following:

  • Wait until no data hazards, then read operands

  • Wait until no control hazards, then read operands

  • Wait until no structural hazards, then read operands

Explanation

Question 100 of 184

1

How many Optimizations’ in Cache memory Performance?

Select one of the following:

  • 10

  • 8

  • 6

Explanation

Question 101 of 184

1

What is the Compulsory in main categories in Cache Memory?

Select one of the following:

  • first-reference to a block, occur even with infinite cache

  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Explanation

Question 102 of 184

1

What is the Capacity in main categories in Cache Memory?

Select one of the following:

  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

  • first-reference to a block, occur even with infinite cache

  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Explanation

Question 103 of 184

1

What is the Conflict in main categories in Cache Memory?

Select one of the following:

  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

  • first-reference to a block, occur even with infinite cache

  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Explanation

Question 104 of 184

1

What is the Temporal Locality?

Select one of the following:

  • Exploit by remembering the contents of recently accessed locations

  • Exploit by fetching blocks of data around recently accessed locations

Explanation

Question 105 of 184

1

What is the Spatial Locality?

Select one of the following:

  • Exploit by fetching blocks of data around recently accessed locations

  • Exploit by remembering the contents of recently accessed locations

Explanation

Question 106 of 184

1

What is the Reducing the Hit time?

Select one of the following:

  • Small and simple first-level caches and way-prediction

  • Pipelined caches, multibanked caches, and nonblocking caches

  • Critical word first and merging write buffer

Explanation

Question 107 of 184

1

What is the Increasing cache bandwidth?

Select one of the following:

  • Pipelined caches, multibanked caches, and nonblocking caches

  • Small and simple first-level caches and way-prediction

  • Critical word first and merging write buffer

Explanation

Question 108 of 184

1

What is the Reducing the Miss Penalty?

Select one of the following:

  • Critical word first and merging write buffer

  • Small and simple first-level caches and way-prediction

  • Pipelined caches, multibanked caches, and nonblocking caches

Explanation

Question 109 of 184

1

What is the Reducing the Miss Rate?

Select one of the following:

  • Compiler Optimization

  • Time Optimization

  • Performance Optimization

Explanation

Question 110 of 184

1

Main term of dependability is SLAs?

Select one of the following:

  • Service level agreements

  • Standard level achievement

  • Scale level approach

Explanation

Question 111 of 184

1

Main term of dependability is SLOs?

Select one of the following:

  • Service level objectives

  • Standard level offset

Explanation

Question 112 of 184

1

The second type of dependence is?

Select one of the following:

  • Name dependence

  • Data dependence

  • Control dependence

Explanation

Question 113 of 184

1

RAW (read after write)?

Select one of the following:

  • This hazard is the most common type and corresponds to a true data dependence

  • This hazard corresponds to an output dependence

  • This hazard arises from an antidependence (or name dependence)

Explanation

Question 114 of 184

1

WAW (write after write)?

Select one of the following:

  • This hazard corresponds to an output dependence

  • This hazard is the most common type and corresponds to a true data dependence

  • This hazard arises from an antidependence (or name dependence)

Explanation

Question 115 of 184

1

WAR (write after read)?

Select one of the following:

  • This hazard corresponds to an output dependence

  • This hazard is the most common type and corresponds to a true data dependence

  • This hazard arises from an antidependence (or name dependence)

Explanation

Question 116 of 184

1

What is the element “Read Operands” in simple five-stage pipeline?

Select one of the following:

  • Decode instructions, check for structural hazards

  • Wait until no data hazards, then read operands

Explanation

Question 117 of 184

1

What is the ROB?

Select one of the following:

  • Reorder buffer

  • Read only buffer

  • Relocate buffer

Explanation

Question 118 of 184

1

How many steps in instruction execution?

Select one of the following:

  • 6

  • 5

  • 3

  • 4

Explanation

Question 119 of 184

1

How many restrictions RAW hazards through memory are maintained?

Select one of the following:

  • 2

  • 3

  • 4

Explanation

Question 120 of 184

1

How many major flavors in Multiple-issue processors?

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 121 of 184

1

How many functions at Integrated Instruction Fetch Units

Select one of the following:

  • 3

  • 4

  • 5

Explanation

Question 122 of 184

1

Speculation and the Challenge of Energy Efficiency consume excess energy in how many ways?

Select one of the following:

  • 2

  • 3

  • 4

Explanation

Question 123 of 184

1

The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?

Select one of the following:

  • 5

  • 4

  • 6

Explanation

Question 124 of 184

1

Infinite register renaming at The Hardware Model?

Select one of the following:

  • There are an infinite number of virtual registers available

  • Branch prediction is perfect, all conditional branches are predicted exactly

Explanation

Question 125 of 184

1

Perfect Branch Prediction at the Hardware Model?

Select one of the following:

  • There are an infinite number of virtual registers available

  • Branch prediction is perfect, all conditional branches are predicted exactly

Explanation

Question 126 of 184

1

Perfect caches at The Hardware Model?

Select one of the following:

  • All memory accesses take one clock cycle

  • All memory addresses are known exactly

  • All conditional branches are predicted exactly

Explanation

Question 127 of 184

1

Perfect memory address alias analysis at The Hardware Model?

Select one of the following:

  • All memory addresses are known exactly

  • All memory accesses take one clock cycle

  • All conditional branches are predicted exactly

Explanation

Question 128 of 184

1

Perfect jump prediction at The Hardware Model?

Select one of the following:

  • All jumps are perfectly predicted

  • All conditional branches are predicted exactly

  • All memory addresses are known exactly

Explanation

Question 129 of 184

1

What is Personal mobile device (PMD)?

Select one of the following:

  • A collection of wireless devices with multimedia user interfaces

  • A collection of computers with wireless network adapters

  • A collection of Clusters/Warehouse-scale computers

Explanation

Question 130 of 184

1

Where the embedded microprocessors are used?

Select one of the following:

  • In microwaves, washing machines

  • In Personal Computers

  • In mobile phones

Explanation

Question 131 of 184

1

What functions has Instruction Set Architecture (ISA)?

Select one of the following:

  • Serves as the boundary between the software and hardware?

  • Serves as the bridge between CPU and Memory

  • o Serves as the bridge between CPU and Cache

Explanation

Question 132 of 184

1

What is the TLP?

Select one of the following:

  • Time Level Parallelism

  • Technology Level Parallelism

  • Task Level Parallelism

Explanation

Question 133 of 184

1

By Moore's law, growth rate in transistor count on a chip is doubling?

Select one of the following:

  • every 8 to 12 months

  • every 12 to 16 months

  • every 18 to 24 months

Explanation

Question 134 of 184

1

How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?

Select one of the following:

  • 3

  • 2

  • 4

Explanation

Question 135 of 184

1

What is the “Module reliability” in Dependability?

Select one of the following:

  • A measure of the continuous service accomplishment from a reference initial instant

  • a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.

  • a measure of the interruption

Explanation

Question 136 of 184

1

What is response time?

Select one of the following:

  • the time between the start and the completion of an event

  • The time to get an information

  • The time spent on execution of a program

Explanation

Question 137 of 184

1

The guiding principle of reporting performance measurements should be?

Select one of the following:

  • reproducibility

  • responsibility

  • creativity

Explanation

Question 138 of 184

1

What is Temporal Locality?

Select one of the following:

  • recently accessed items are likely to be accessed in the near future

  • items whose addresses are near one another tend to be referenced close together in time

  • the nearest data stored in secondary memory

Explanation

Question 139 of 184

1

What is Spatial Locality?

Select one of the following:

  • items whose addresses are near one another tend to be referenced close together in time

  • recently accessed items are likely to be accessed in the near future

  • the nearest data stored in secondary memory

Explanation

Question 140 of 184

1

What is Amdahl's law?

Select one of the following:

  • Defines the speedup that can be gained by using a particular feature

  • Defines time spent on execution of a program

  • Defines data gained in one operation

Explanation

Question 141 of 184

1

The most popular scheme is set associative, where a set is?

Select one of the following:

  • a group of blocks

  • a group of instructions

  • a group of comparatives

Explanation

Question 142 of 184

1

The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?

Select one of the following:

  • The very first access to a block cannot be in the cache, so the block must be brought into the cache

  • If the cache cannot contain all the blocks needed during execution of a program

  • If the block placement strategy is not fully associative

Explanation

Question 143 of 184

1

The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?

Select one of the following:

  • If the cache cannot contain all the blocks needed during execution of a program

  • The very first access to a block cannot be in the cache, so the block must be brought into the cache

  • If the block placement strategy is not fully associative

Explanation

Question 144 of 184

1

The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?

Select one of the following:

  • If the block placement strategy is not fully associative

  • The very first access to a block cannot be in the cache, so the block must be brought into the cache

  • If the cache cannot contain all the blocks needed during execution of a program

Explanation

Question 145 of 184

1

The “natural” unit of organization of memory:

Select one of the following:

  • Word

  • Document

  • Several Computer

Explanation

Question 146 of 184

1

Main element of cache memory is …

Select one of the following:

  • Line

  • Word

  • String

Explanation

Question 147 of 184

1

Typical levels of Cache memories …

Select one of the following:

  • 1,2,3 levels

  • 1,2,3,4,5 levels

  • Cache memories have no levels

Explanation

Question 148 of 184

1

Select internal memory …

Select one of the following:

  • Hard Disk

  • CD-ROM

  • Processor registers

Explanation

Question 149 of 184

1

Select internal memory

Select one of the following:

  • Hard Disk

  • Optical disk

  • Main memory

Explanation

Question 150 of 184

1

Select internal memory

Select one of the following:

  • Cache

  • Magnetic tape

  • Optical disks

Explanation

Question 151 of 184

1

Select external memory:

Select one of the following:

  • Processor registers

  • Cache

  • Main memory

  • Hard disks

Explanation

Question 152 of 184

1

Select external memory

Select one of the following:

  • Optical Disk

  • Cache level 1

  • Registers of processor

Explanation

Question 153 of 184

1

Select external memory

Select one of the following:

  • Magnetic tape

  • Main memory

  • All cache memories

Explanation

Question 154 of 184

1

Physical types of memories:

Select one of the following:

  • Direct, Random

  • Direct, Access time

  • Semiconductor, Optical

Explanation

Question 155 of 184

1

Physical types of memories:

Select one of the following:

  • Semiconductor, Magnetic

  • Word, Block

  • Direct, Random

Explanation

Question 156 of 184

1

Physical types of memories:

Select one of the following:

  • Magneto-optical

  • Number of words

  • Number of bytes

Explanation

Question 157 of 184

1

Select correct memory hierarchy:

Select one of the following:

  • Cache – Main Memory – Secondary storages

  • Secondary storages - Cache – Main Memory

  • Main Memory – Cache - Secondary storages

Explanation

Question 158 of 184

1

Select correct memory hierarchy:

Select one of the following:

  • Processor registers – Cache memory – Main memory

  • Cache memory – Main memory - Processor registers

  • Cache memory – Processor registers - Main memory

Explanation

Question 159 of 184

1

External, nonvolatile memory is also referred to as …

Select one of the following:

  • Auxiliary memory

  • Main memory

  • Levels of cache

Explanation

Question 160 of 184

1

Types of cache addresses:

Select one of the following:

  • Logical, Physical

  • Direct, Associative

  • Set Associative

Explanation

Question 161 of 184

1

A logical cache stores data using …

Select one of the following:

  • virtual addresses

  • virtual addresses and physical addresses

  • Physical addresses

Explanation

Question 162 of 184

1

The two basic forms of semiconductor random access memory are:

Select one of the following:

  • dynamic RAM (DRAM) and static RAM (SRAM)

  • magnetic and optical

  • Winchester and optical disks

Explanation

Question 163 of 184

1

Main element of cache memory?

Select one of the following:

  • Tag

  • Word

  • String

Explanation

Question 164 of 184

1

A number of chips can be grouped together to form …

Select one of the following:

  • a memory bank

  • a memory tags

  • a memory lines

Explanation

Question 165 of 184

1

Data are recorded on and later retrieved from the disk via a conducting coil named:

Select one of the following:

  • The arm

  • The slide

  • The head

Explanation

Question 166 of 184

1

The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …

Select one of the following:

  • multiple zoned recording

  • intersector gap

  • the constant angular velocity

Explanation

Question 167 of 184

1

To increase density, modern hard disk systems use a technique known as:

Select one of the following:

  • multiple zone recording

  • the constant angular velocity

Explanation

Question 168 of 184

1

… can be removed and replaced with another disk.

Select one of the following:

  • Processor registers

  • A non-removable disk

  • A removable disk

Explanation

Question 169 of 184

1

For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...

Select one of the following:

  • double sided

  • single sided

  • no sides

Explanation

Question 170 of 184

1

The set of all the tracks in the same relative position on the platter is referred to as …

Select one of the following:

  • a cylinder

  • a square

  • a circle

Explanation

Question 171 of 184

1

On a movable head system, the time it takes to position the head at the track is known as …

Select one of the following:

  • transfer time

  • access time

  • seek time

Explanation

Question 172 of 184

1

The operating system …

Select one of the following:

  • is the software that controls the execution of programs on a processor and that manages the processor’s resources.

  • is one which is understandable by us humans

  • is a collection of Clusters/Warehouse-scale computers

  • a program that directly executes instructions written in a programming language

Explanation

Question 173 of 184

1

The most important functions of the Operating System are:

Select one of the following:

  • The scheduling of processes, or tasks

  • Compile C++ program codes

  • Interpret PHP program codes

  • Provide drivers for the remote devices

Explanation

Question 174 of 184

1

The important function of the Operating System is

Select one of the following:

  • Memory management

  • Provide compiler for high level programming languages

  • Increase size of cache

Explanation

Question 175 of 184

1

How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…

Select one of the following:

  • Program execution

  • Access to I/O devices

  • Program creation

Explanation

Question 176 of 184

1

How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.

Select one of the following:

  • Program creation

  • Access to I/O devices

  • Program execution

Explanation

Question 177 of 184

1

How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.

Select one of the following:

  • Access to I/O devices

  • Program execution

  • Program creation

Explanation

Question 178 of 184

1

How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.

Select one of the following:

  • Controlled access to files

  • Access to I/O devices

  • System access

Explanation

Question 179 of 184

1

How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.

Select one of the following:

  • Error detection and response

  • System access

  • Controlled access to files

Explanation

Question 180 of 184

1

How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.

Select one of the following:

  • Accounting

  • System access

  • Controlled access to files

Explanation

Question 181 of 184

1

Select two independent dimensions of the Operating System:

Select one of the following:

  • batch and interactive

  • batch and computer operator

  • Interactive and computer operator

Explanation

Question 182 of 184

1

Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.

Select one of the following:

  • Access Permission (AP), Access Permission Extension (APX)

  • Bufferable (B) bit

  • Cacheable (C) bit

Explanation

Question 183 of 184

1

Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.

Select one of the following:

  • Bufferable (B) bit

  • Cacheable (C) bit

  • Type Extension (TEX)

Explanation

Question 184 of 184

1

Different types of parallelism in applications like:

Select one of the following:

  • Data-level Parallelism

  • Task-level Parallelism

  • Instruction-level Parallelism

  • All of the above

Explanation

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