Copy and Edit

БАЗА Вопросы с Чаптеров

Description

It always seems impossible until it’s done.
Csse 1502
Quiz by Csse 1502, updated more than 1 year ago
Csse 1502
Created by Csse 1502 over 6 years ago
44
1
0

Resource summary

Question 1

Question
Which of the following descriptions corresponds to static power?
Answer
  • Proportional to the product of the number of switching transistors and the switching rate
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Dominant energy consumer
  • All of the above

Question 2

Question
Which of the following descriptions corresponds to dynamic power?
Answer
  • Proportional to the product of the number of switching transistors and the switching rate
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Certainly a design concern
  • None of the above

Question 3

Question
Which of the written below is NOT increase power consumption?
Answer
  • Increasing performance
  • Increasing multiple cores
  • Increasing multithreading
  • Decreasing performance

Question 4

Question
Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when
Answer
  • The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
  • The number of transistors switching will be proportional to the sustained rate, and the performance is proportional to the peak issue rate
  • The number of transistors switching will be proportional to the sustained rate
  • The performance is proportional to the peak issue rate

Question 5

Question
How this process called: “Operations execute as soon as their operands are available”
Answer
  • data flow execution
  • instruction execution
  • data control execution
  • instruction field execution

Question 6

Question
If we want to sustain four instructions per clock
Answer
  • We must fetch less, issue more, and initiate execution on more than two instructions
  • We must fetch more, issue less, and initiate execution on more than three instructions
  • We must fetch more, issue more, and initiate execution on more than four instructions
  • We must fetch more, issue more, and initiate execution on less than five instructions

Question 7

Question
For what the reorder buffer is used :
Answer
  • To pass parameters through instructions that may be speculated
  • To pass results among instructions that may be speculated.
  • To get additional registers in the same way as the reservation stations
  • To control registers

Question 8

Question
How many fields contains the entry in the ROB:
Answer
  • 5
  • 6
  • 3
  • 4

Question 9

Question
Choose correct fields of entry in the ROB:
Answer
  • the source type, the destination field, the value field, and the ready field
  • the program type, the ready field, the parameter field, the destination field
  • the instruction type, the destination field, the value field, and the ready field
  • the instruction type, the destination field, and the ready field

Question 10

Question
Choose the steps of instruction execution:
Answer
  • issue, execute, write result, commit
  • execution, commit, rollback
  • issue, execute, override, exit
  • begin, write, interrupt, commit

Question 11

Question
Which Multiple-issue processors has not the hardware hazard detection:
Answer
  • Superscalar(dynamic)
  • Superscalar(static)
  • Superscalar(speculative)
  • EPIC

Question 12

Question
Examples of EPIC:
Answer
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • MIPS and ARM
  • TI C6x

Question 13

Question
Examples of superscalar(static):
Answer
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • MIPS and ARM
  • TI C6x

Question 14

Question
If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Answer
  • Static power
  • Dynamic power
  • Processing rate
  • Processor state

Question 15

Question
Examples of superscalar(dynamic) :
Answer
  • Pentium 4, MIPS R12K, IBM, Power5
  • None at the present
  • MIPS and ARM
  • TI C6x

Question 16

Question
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Answer
  • Static power
  • Dynamic power
  • Processing rate
  • Processor state

Question 17

Question
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Answer
  • Limited ILP due to software dependences
  • Achievable ILP with hardware resource constraints
  • Variability of ILP due to software and hardware interaction
  • Achievable ILP with software resource constraints

Question 18

Question
Examples of VLIW/LIW:
Answer
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • MIPS and ARM
  • TI C6x

Question 19

Question
What is a hash table?
Answer
  • Popular data structure for updating large collections, so that one can hardly answer questions
  • Popular tables for organizing a large collection of data structure
  • Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • Popular data structure for deleting small collections of data items so that one can hardly answer questions

Question 20

Question
A branch-prediction cache that stores the predicted address for the next instruction after a branch
Answer
  • branch-target buffer
  • data buffer
  • framebuffer
  • optical buffer

Question 21

Question
Buffering the actual target instructions allows us to perform an optimization which called:
Answer
  • branch folding
  • Branch prediction
  • Target instructions
  • Target address

Question 22

Question
Which of these is NOT characteristics of recent highperformance microprocessors?
Answer
  • Power
  • Functional unit capability
  • Clock rate
  • Color

Question 23

Question
Which is not the function of integrated instruction fetch unit:
Answer
  • Integrated branch prediction
  • Instruction prefetch
  • Instruction memory access and buffering
  • Instruction memory commit

Question 24

Question
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Answer
  • Address aliasing prediction
  • Branch prediction
  • Integrated branch prediction
  • Dynamic branch prediction

Question 25

Question
How to decrypt RISC?
Answer
  • Reduced Instruction Set Computer
  • Recall Instruction Sell Communication
  • Rename Instruction Sequence Corporation
  • Red Instruction Small Computer

Question 26

Question
The ideal pipeline CPI is a measure of …
Answer
  • the maximum performance attainable by the instruction
  • the minimum performance attainable by the implementation
  • the maximum performance attainable by the implementation
  • the minimum performance attainable by the instruction

Question 27

Question
what is the Pipeline CPI = ?
Answer
  • deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • deal pipeline CPU + Data hazard stalls + Control stalls
  • deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
  • Structural stalls + Data hazard stalls + Control stalls

Question 28

Question
The simplest and most common way to increase the ILP is …?
Answer
  • to exploit minimalism among iterations of a loop
  • to exploit parallelism among iterations of a loop
  • to destroy iterations of a loop
  • to decrease the minimalism of risk

Question 29

Question
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Answer
  • exploit-level parallelism
  • high-level minimalism
  • loop-level parallelism
  • low-level minimalism

Question 30

Question
In parallelism have three different types of dependences, tagging him:
Answer
  • data dependences , name dependences , and control dependences .
  • data dependences , name dependences , and surname dependences .
  • datagram dependences , name dependences , and animal dependences .
  • no correct answers

Question 31

Question
What is Name dependence?
Answer
  • name dependence occurs when two instructions use the same register or memory location
  • name dependence occurs when five or more instructions use the same register or memory location
  • name dependence occurs when instructions use the same name
  • All answers is correct

Question 32

Question
When occurs an output dependence?
Answer
  • when i and instruction j write the same name
  • when i and instruction j write the same register or memory location
  • when i and instruction j write the same adress or memory location
  • All answers is correct

Question 33

Question
What is RAW (read after write)?
Answer
  • when j tries to read a source before i writes it, so j incorrectly gets the old value
  • when i tries to read a source before j writes it, so j correctly gets the old value
  • when j tries to write a source before i writes it
  • when a tries to write a source before b read it, so a incorrectly gets the old value

Question 34

Question
What is given is not a hazard?
Answer
  • WAR
  • RAR
  • WAW
  • LOL

Question 35

Question
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Answer
  • loop-level
  • RAR
  • loop rolling
  • loop unrolling

Question 36

Question
Effect that results from instruction scheduling in large code segments is called…?
Answer
  • loop unrolling
  • loop-level
  • register pressure
  • registration

Question 37

Question
The simplest dynamic branch-prediction scheme is a
Answer
  • branch-prediction buffer
  • branch buffer
  • All answers correct
  • no correct answers

Question 38

Question
Branch predictors that use the behavior of other branches to make a prediction are called
Answer
  • correlating predictors or two-level predictors
  • branch-prediction buffer
  • branch table
  • three level loop

Question 39

Question
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Answer
  • the number of prediction entries selected by the branch = 1K.
  • the number of prediction entries selected by the branch = 2K.
  • the number of prediction entries selected by the branch = 8K.
  • the number of prediction entries selected by the branch = 4K.

Question 40

Question
What is the compulsory in Cs model?
Answer
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The number of accesses that miss divided by the number of accesses.
  • None of these

Question 41

Question
What is capacity in Cs model?
Answer
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • The number of accesses that miss divided by the number of accesses.
  • None of these

Question 42

Question
What is conflict in Cs model?
Answer
  • If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • None of these

Question 43

Question
Choose the benefit of Cache Optimization.
Answer
  • Larger block size to reduce miss rate
  • Bigger caches to increase miss rat
  • Single level caches to reduce miss penalty
  • None of these

Question 44

Question
Choose the strategy of Seventh Optimization.
Answer
  • Critical word first
  • Critical restart
  • Sequential interleaving
  • Merging Write Buffer to Reduce Miss Penalty

Question 45

Question
Choose the Eight Optimization
Answer
  • Merging Write Buffer to Reduce Miss Penalty
  • Critical word first
  • Nonblocking Caches to Increase Cache Bandwidth
  • Trace Caches to Reduce Hit Time

Question 46

Question
Choose the Eleventh Optimization
Answer
  • Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • Merging Write Buffer to Reduce Miss Penalty
  • Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • None of these

Question 47

Question
What is the access time?
Answer
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • None of these

Question 48

Question
9. What is the cycle time?
Answer
  • The minimum time between requests to memory.
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of these

Question 49

Question
What does SRAM stands for?
Answer
  • Static Random Access memory
  • System Random Access memory
  • Short Random Access memory
  • None of these

Question 50

Question
What does DRAM stands for?
Answer
  • Dynamic Random Access memory
  • Dual Random Access memory
  • Dataram Random Access memory
  • None of these

Question 51

Question
What does DDR stands for?
Answer
  • Double data rate
  • Dual data rate
  • Double data reaction
  • None of these

Question 52

Question
What is kernel process?
Answer
  • Provide at least two modes, indicating whether the running process is a user process or an operating system process
  • Provide at least five modes, indicating whether the running process is a user process or an operating system process
  • Provide a portion of the processor state that a user process can use but not write
  • None of these

Question 53

Question
Which one is NOT concerning to pitfall?
Answer
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Overemphasizing memory bandwidth in DRAMs
  • Predicting cache performance of one program from another

Question 54

Question
Which one is concerning to fallacy?
Answer
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Predicting cache performance of one program from another
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Overemphasizing memory bandwidth in DRAMs
Show full summary Hide full summary

Want to create your own Quizzes for free with GoConqr? Learn more.

Similar

3. The Bolshevik's Seizure of Power
ShreyaDas
A Level: English language and literature techniques = Structure
Jessica 'JessieB
A2 Ethics - Virtue Ethics
Heloise Tudor
ICT Key Terms Quiz - Part 1
Mr Mckinlay
Modern Studies - Democracy in Scotland/UK.
Daniel Cormack
Physics 1A - Energy
Zaki Rizvi
Using GoConqr to study Maths
Sarah Egan
New English Literature GCSE
Sarah Egan
Macbeth Quotes/Themes
Michael LEwis
An Inspector Calls - Quotes and Context
James Holder
General Pathoanatomy Final MCQs (1-110)- 3rd Year- PMU
Med Student
Browse Library