11797365
Descripción
Test por Hello World, actualizado hace más de 1 año
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Creado por Hello World
hace casi 7 años
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Pregunta 1
Pregunta
130. How many bytes equals Petabyte (PB)?
Respuesta
-
· Quadrillion
-
· Million
-
· Trillion
-
· Billion
-
· 1000
Pregunta 2
Pregunta
129. Which one of the following is a memory whose duty is to store most frequently used data?
Respuesta
-
· Main memory
-
· Cache
-
· ROM
-
· Auxiliary memory
-
· PROM
Pregunta 3
Pregunta
128. The digital circuit that generates the arithmetic sum of two binary numbers of any length is ___.
Respuesta
-
· Binary Adder
-
· Full Adder
-
· Half Adder
-
· Adder
-
· OR gate
Pregunta 4
Pregunta
127. The key technology used in IV generation computers is ___.
Respuesta
-
· MSI
-
· SSI
-
· LSI & VLSI
-
· Transistors
-
· Vacuum Tubes
Pregunta 5
Pregunta
126. The computer architecture having stored program is ___.
Respuesta
-
· Harvard
-
· Von Neumann
-
· Pascal
-
· Ada
-
· Cobol
Pregunta 6
Pregunta
125. Stack is a ___list.
Respuesta
-
· FIFO
-
· LIFO
-
· FILO
-
· OFLI
Pregunta 7
Pregunta
124. CACHE memory is implemented using ___.
Respuesta
-
· Dynamic RAM
-
· Static RAM
-
· EA RAM
-
· ED RAM
-
· EP RAM
Pregunta 8
Pregunta
123. What does D stand for in a D flip-flop?
Respuesta
-
· Direct
-
· Don’t care
-
· Data
-
· Device
-
· Disk
Pregunta 9
Pregunta
104. What is a Capacity?
Respuesta
-
· cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
· first-reference to a block, occur even with infinite cache
-
· misses that occur because of collisions due to less than full associativity
Pregunta 10
Pregunta
103. What is a Compulsory?
Respuesta
-
· first-reference to a block, occur even with infinite cache
-
· cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
· misses that occur because of collisions due to less than full associativity
Pregunta 11
Pregunta
39. 74. How many elements of the Instruction Set Architecture (ISA)
Respuesta
-
8
-
7
-
6
Pregunta 12
Pregunta
38. 73. What is the MISD one of the categories of computers?
Respuesta
-
Multiple Instruction Streams, Multiple Data Streams
-
Multiple Instructions Streams, Single Data Stream
-
Multiple Instruction Streams, Set Data Stream
Pregunta 13
Pregunta
36. 72. What is the Instruction Level Parallelism
Respuesta
-
Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
Pregunta 14
Pregunta
35. 71. What is the Request Level Parallelism
Respuesta
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
Pregunta 15
Pregunta
34. 70. What is the Thread Level Parallelism
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Pregunta 16
Pregunta
33. 69. What is the Vector Architectures and Graphic Processor Units (GPUs)
Respuesta
-
Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
Pregunta 17
Pregunta
32. 68. The Application of Brokerage operations how many cost of downtime per hour?
Respuesta
-
8.870.000$
-
7.550.000$
-
6.450.000$
Pregunta 18
Pregunta
31. 67. What is the PMD in computer classes?
Respuesta
-
Percentage map device
-
Personal mobile device
-
Peak maze development
-
Powerful markup distance
Pregunta 19
Pregunta
30. 66. Which distance of price has Clusters/warehouse-scale computers?
Respuesta
-
100 – 100.000$
-
100.000 – 200.000.000$
-
5.000 – 10.000.000$
Pregunta 20
Pregunta
29. 65. How many classes of computers classified?
Respuesta
-
7
-
3
-
5
Pregunta 21
Pregunta
28. 64. What is the RLP?
Respuesta
-
Request Level Parallelism
-
Research Level Parallelism
-
Random Level Parallelism
Pregunta 22
Pregunta
27. 63. How much in percentage single-processor performance improvement has dropped to less than?
Respuesta
-
22%
-
33%
-
11%
Pregunta 23
Pregunta
26. 62. When single-processor performance improvement has dropped?
Respuesta
-
2003
-
2002
-
2004
Pregunta 24
Pregunta
25. 61. What is a RISC computers?
Respuesta
-
Rational Interruptible Security Computer
-
Research Interconnect Several Computer
-
Reduced Instruction Set Computer
Pregunta 25
Pregunta
24. 56. Choose the right formula of AMAT(в базе был неверный ответ можете попробовать подать апелляцию)
Respuesta
-
Average Memory Access time = Hit Time + Miss Rate * Miss penalty
-
Average Memory Access time = Hit Rate + Miss Rate * Miss penalty
-
Average Memory Access time = Hit Time + Miss time * Miss penalty
-
Average Memory Access time = Hit Rate + Miss time * Miss penalty
Pregunta 26
Pregunta
23. What is the total number of writes that hit in the cache?
Respuesta
-
588
-
784
-
12.5%
-
0.25%
Pregunta 27
Pregunta
22. 30. Definition of Block address:
Respuesta
-
minimum unit that is presented or not present
-
location of block in memory
-
percentage of item not found in upper level
-
time to access upper level
-
memory closer to processor
Pregunta 28
Pregunta
20. 28. Definition of Block:
Respuesta
-
minimum unit that is presented or not present
-
location of block in memory
-
percentage of item not found in upper level
-
memory closer to processor
-
time to access upper level
Pregunta 29
Pregunta
19. 27. What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
Respuesta
-
SRAM
-
DRAM
-
RAM
Pregunta 30
Pregunta
18. 26. Performance of a machine is determined by:
Respuesta
-
Instruction count, Clock cycle time, Correlating predictors
-
Instruction count, Clock cycle time, Clock cycle per instruction
-
Clock cycle time, Correlating predictors, Aggressive instruction
-
Clock cycle time, Clock cycles per instruction, Correlating Predictors
Pregunta 31
Pregunta
17. 25. Pipe-lining is a unique feature of ___.
Respuesta
-
CISC
-
IANA
-
ISA
-
RISC
Pregunta 32
Pregunta
16. 24. The iconic feature of the RISC machine among the following are
Respuesta
-
Increased memory size
-
Reduced number of addressing modes
-
Having a branch delay slot
-
All of the above
Pregunta 33
Pregunta
15. 23. The Sun micro systems processors usually follow ___ architecture.
Respuesta
-
CISC
-
ISA
-
ULTRA SPARC
-
RISC
Pregunta 34
Pregunta
14. 22. Of the following, identify the memory usually written by the manufacturer.
Respuesta
-
RAM
-
DRAM
-
SRAM
-
ROM
-
Cache Memory
Pregunta 35
Pregunta
13. 21. What do you call the given statement as “The number successful accesses to memory stated as a fraction.”
Respuesta
-
Hit rate
-
Miss rate
-
Access rate
-
Success rate
Pregunta 36
Pregunta
12. 20. How many instructions can be implemented in MIPS?
Respuesta
-
2 clock cycles
-
3 clock cycles
-
4 clock cycles
-
5 clock cycles
Pregunta 37
Pregunta
19. The secondary effect that results from instruction scheduling in large code segments is called ___?
Respuesta
-
Aggressive instruction
-
Correlating predictors
-
Register predictors
-
Register pressure
Pregunta 38
Pregunta
10. 18. The CISC stands for?
Respuesta
-
Computer Instruction Set Compliment
-
Complete Instruction Set Compliment
-
Computer Indexed Set Components
-
Complex Instruction Set Computer
Pregunta 39
Pregunta
9. Assembly line operation is also called as?
Respuesta
-
Pipelining process
-
Superscalar operation
-
None of the mentioned
-
Von Neumann cycle
Pregunta 40
Pregunta
8. 16. Can you solve the Dining Philosophers’ Problem using monitors?
Respuesta
-
Yes
-
No
-
Yes, but only if there are less than five philosophers
-
No, unless there are more than five philosophers
Pregunta 41
Pregunta
7. 15. The central themes of operating system design are all concerned with the management of processes and threads?
Respuesta
-
Multiprogramming, multiprocessing, distributed processing
-
Multitasking, multiprogramming, multithreading
-
Multiprocessing, uniprocessing, multitasking
-
Multithreading, distributed processing, uniprocessing
Pregunta 42
Pregunta
6. 14. Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Respuesta
-
Availability, confidentiality, data integrity, authenticity
-
Safety, accountability, reliability, density
-
Usability, integrity, confidentiality, reliability
-
Flexibility, availability, accountability, authenticity
Pregunta 43
Pregunta
5. 13. Which of the following principles has Deadlock?
Respuesta
-
Execution, Association, Starvation
-
Prevention, Avoidance, Detection
-
Starvation, Detection, Exclusion
-
Exclusion, Avoidance, Starvation
Pregunta 44
Pregunta
4. 12. How many principles has Deadlock?
Respuesta
-
3
-
5
-
2
-
6
Pregunta 45
Pregunta
3. 11. Three techniques are possible for I/O operations:
Respuesta
-
Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
-
Machine I/O, Architecture I/O, Hardware I/O
-
Object-oriented I/O, Design I/O, Usable I/O
-
Control I/O, Status I/O, Transfer I/O
Pregunta 46
Pregunta
2. 10. Cache Design has these properties?
Respuesta
-
Size, search function, write function, read policy, vector algorithm
-
Size, mapping algorithm, vector function, write policy, replacement function
-
Size, blocking algorithm, search function, replacement vector, read policy
-
Size, block size, mapping function, replacement algorithm, write policy
Pregunta 47
Pregunta
1. In Memory Hierarchy, at the Inboard storage which of the following are included:
Respuesta
-
Magnetic disk
-
Magnetic tape
-
Optical disk
-
Main memory
Pregunta 48
Pregunta
180. In Memory Hierarchy, at the Off-line storage which of the following are included:
Respuesta
-
• Cache
-
• Magnetic disk
-
• Magnetic tape
-
• Main memory
Pregunta 49
Pregunta
179. In Memory Hierarchy, at the Outboard storage which of the following are included:
Respuesta
-
• Cache
-
• Main memory
-
• Magnetic tape
-
• Magnetic disk
Pregunta 50
Pregunta
178. How many parts of Memory Hierarchy?
Respuesta
-
• 5
-
• 4
-
• 2
-
• 3
Pregunta 51
Pregunta
177. Which one is concerning to fallacy?
Respuesta
-
o Predicting cache performance of one program from another
-
o Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
o Over emphasizing memory bandwidth in DRAMs
Pregunta 52
Pregunta
176. Which one is NOT concerning to pitfall?
Respuesta
-
o Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
o Over emphasizing memory bandwidth in DRAMs
-
o Predicting cache performance of one program from another
Pregunta 53
Pregunta
175. ChoosetheEleventhOptimization
Respuesta
-
o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
-
o Merging Write Buffer to Reduce Miss Penalty
-
o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
-
o None of them
Pregunta 54
Pregunta
174. ChoosetheEightOptimization
Respuesta
-
o Merging Write Buffer to Reduce Miss Penalty
-
o Critical word first
-
o Nonblocking Caches to Increase Cache Bandwidth
-
o Trace Caches to Reduce Hit Time
Pregunta 55
Pregunta
173. Choose the strategy of Seventh Optimization.
Respuesta
-
o Critical restart
-
o Critical word first
-
o Sequential inter leaving
-
o Merging Write Buffer to Reduce Miss Penalty
Pregunta 56
Pregunta
172. Choose the benefit of Cache Optimization.
Respuesta
-
o Larger block size to reduce miss rate
-
o Bigger caches to increase miss rat
-
o Single level caches to reduce miss penalty
-
o None of them
Pregunta 57
Pregunta
171. What is conflict in Cs model?
Respuesta
-
o If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
-
o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
o None of them
Pregunta 58
Pregunta
170. What is capacityin Cs model?
Respuesta
-
o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
o The number of accesses that miss divided by the number of accesses.
-
o None of them
Pregunta 59
Pregunta
169. What is the compulsory in Cs model?
Respuesta
-
o The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
o The number of accesses that miss divided by the number of accesses.
-
o None of them
-
o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
Pregunta 60
Pregunta
168. How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Respuesta
-
o the number of prediction entries selected by the branch = 1K.
-
o the number of prediction entries selected by the branch = 2K.
-
o the number of prediction entries selected by the branch = 8K.
-
o the number of prediction entries selected by the branch = 4K.
Pregunta 61
Pregunta
167. Branch predictors that use the behavior of other branches to make a prediction are called
Respuesta
-
o correlating predictors or two-level predictors
-
o branch-prediction buffer
-
o branch table
-
o three level loop
Pregunta 62
Pregunta
166. The simplest dynamic branch-prediction scheme is a
Respuesta
-
o branch-prediction buffer
-
o branch buffer
-
o All answers correct
-
o registrationo registration
Pregunta 63
Pregunta
165. Effect that results from instruction scheduling in large code segments is called…?
Respuesta
-
o register pressure
-
o loop unrolling
-
o loop-level
-
o registration
Pregunta 64
Pregunta
164. A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Respuesta
-
o loop unrolling
-
o RAR
-
o loop-level
-
o loop rolling
Pregunta 65
Pregunta
163. What is given is not a hazard?
Respuesta
-
o RAR
-
o WAR
-
o WAW
-
o LOL
Pregunta 66
Pregunta
162. What is RAW (read after write)?
Respuesta
-
o when j tries to read a source before i writes it, so j incorrectly gets the old value
-
o when j tries to write a source before i writes it
-
o when i tries to read a source before j writes it, so j correctly gets the old value
-
o when a tries to write a source before b read it, so a incorrectly gets the old value
Pregunta 67
Pregunta
161. When occurs an output dependence?
Respuesta
-
o When i and instruction j write the same register or memory location
-
o when i and instruction j write the same adress or memory location
-
o when i and instruction j write the same name
-
o All answers is correct
Pregunta 68
Pregunta
160. What is Name dependence?
Respuesta
-
o name dependence occurs when two instructions use the same register or memory location
-
o name dependence occurs when five or more instructions use the same register or memory location
-
o name dependence occurs when instructions use the same name
-
o All answers is correct
Pregunta 69
Pregunta
159. In parallelism have three different types of dependences, tagging him:
Respuesta
-
o data dependences , name dependences , and surname dependences
-
o datagram dependences , name dependences , and animal dependences
-
o no correct answers
-
o data dependences , name dependences , and control dependences
Pregunta 70
Pregunta
158. The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Respuesta
-
o loop-level parallelism
-
o exploit-level parallelism
-
o high-level minimalism
-
o low-level minimalism
Pregunta 71
Pregunta
157. The simplest and most common way to increase the ILP is …?
Respuesta
-
o to exploit parallelism among iterations of a loop
-
o to exploit minimalism among iterations of a loop
-
o to destroy iterations of a loop
-
o to decrease the minimalism of risk
Pregunta 72
Pregunta
156. What is the Pipeline CP = ?
Respuesta
-
o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
-
o deal pipeline CPU + Data hazard stalls + Control stalls
-
o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
-
o Structural stalls + Data hazard stalls + Control stalls
Pregunta 73
Pregunta
155. The ideal pipeline CPI is a measure of …
Respuesta
-
o the maximum performance attainable by the implementation
-
o the maximum performance attainable by the instruction
-
o the minimum performance attainable by the implementation
-
o the minimum performance attainable by the instruction
Pregunta 74
Pregunta
154. How to decrypt RISC?
Respuesta
-
o Reduced Instruction Set Computer
-
o Recall Instruction Sell Communication
-
o Rename Instruction Sequence Corporation
-
o Red Instruction Small Computer
Pregunta 75
Pregunta
153. What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Respuesta
-
o Address aliasing prediction
-
o Branch prediction
-
o Integrated branch prediction
-
o Dynamic branch prediction
Pregunta 76
Pregunta
152. Which is not the function of integrated instruction fetch unit:
Respuesta
-
o Instruction memory commit
-
o Integrated branch prediction
-
o Instruction memory access and buffering
-
o Instruction prefetch
Pregunta 77
Pregunta
151. Buffering the actual target instructions allows us to perform an optimization which called:
Respuesta
-
o branch folding
-
o Branch prediction
-
o Target instructions
-
o Target address
Pregunta 78
Pregunta
150. A branch-prediction cache that stores the predicted address for the next instruction after a branch
Respuesta
-
o branch-target buffer
-
o data buffer
-
o frame buffer
-
o optical buffer
Pregunta 79
Pregunta
149. Examples of VLIW/LIW:
Respuesta
-
o TI C6x
-
o MIPS and ARM
-
o Itanium
-
o Pentium 4, MIPS R12K, IBM, Power5
Pregunta 80
Pregunta
148. Examples of superscalar(dynamic) :
Respuesta
-
o None at the present
-
o Pentium 4, MIPS R12K, IBM, Power5
-
o MIPS and ARM
-
o TI C6x
Pregunta 81
Pregunta
147. Examples of superscalar(static):
Respuesta
-
• MIPS and ARM
-
o Itanium
-
o Pentium 4, MIPS R12K, IBM, Power5
-
o TI C6x
Pregunta 82
Pregunta
146. Examples of EPIC:
Respuesta
-
o Itanium
-
o MIPS and ARM
-
o Pentium 4, MIPS R12K, IBM, Power5
-
o TI C6x
Pregunta 83
Pregunta
145. Which Multiple-issue processors has not the hardware hazard detection:
Respuesta
-
o EPIC
-
o Superscalar(dynamic)
-
o Superscalar(static)
-
o Superscalar(speculative)
Pregunta 84
Pregunta
144. Which one is not the major flavor of Multiple-issue processors:
Respuesta
-
o statistically superscalar processors
-
o dynamically scheduled superscalar processors
-
o statically scheduled superscalar processors
-
o VLIW (very long instruction word) processors
Pregunta 85
Pregunta
143. Choose the steps of instruction execution:
Respuesta
-
o issue, execute, write result, commit
-
o execution, commit, rollback
-
o issue, execute, override, exit
-
o begin, write, interrupt, commit
Pregunta 86
Pregunta
142. Choose correct fields of entry in the ROB:
Respuesta
-
o the instruction type, the destination field, the value field, and the ready field
-
o the source type, the destination field, the value field, and the ready field
-
o the program type, the ready field, the parameter field, the destination field
-
o the instruction type, the destination field, and the ready field
Pregunta 87
Pregunta
141. How many fields contains the entry in the ROB:
Respuesta
-
4
-
6
-
5
-
3
Pregunta 88
Pregunta
140. For what the reorder buffer is used :
Respuesta
-
o To pass parameters through instructions that may be speculated
-
o To pass results among instructions that may be speculated.
-
o To get additional registers in the same way as the reservation stations
-
o To control registers
Pregunta 89
Pregunta
139. How this process called: “Operations execute as soon as their operands are available”
Respuesta
-
o data flow execution
-
o data control execution
-
o instruction execution
-
o instruction field execution
Pregunta 90
Pregunta
138. Which of these is NOT characteristics of recent highperformance microprocessors?
Respuesta
-
o Color
-
o Functional unit capability
-
o Clock rate
-
o Power
Pregunta 91
Pregunta
• Popular data structure for organizing a large collection of data items so that one can quickly
Respuesta
-
o Popular data structure for organizing a large collection of data items so that one can quickly answer questions
-
o Popular tables for organizing a large collection of data structure
-
o Popular data structure for updating large collections, so that one can hardly answer questions
-
o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions
Pregunta 92
Pregunta
136. Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Respuesta
-
o Achievable ILP with software resource constraints
-
o Limited ILP due to software dependences
-
o Achievable ILP with hardware resource constraints
-
o Variability of ILP due to software and hardware interaction
Pregunta 93
Pregunta
135. When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Respuesta
-
o Dynamic power
-
o Processing rate
-
o Static power
-
o Processor state
Pregunta 94
Pregunta
134. If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Respuesta
-
o Static power
-
o Dynamic power
-
o Processing rate
-
o Processor state
Pregunta 95
Pregunta
133. If we want to sustain four instructions per clock
Respuesta
-
o We must fetch more, issue more, and initiate execution on more than four instructions
-
o We must fetch less, issue more, and initiate execution on more than two instructions
-
o We must fetch more, issue more, and initiate execution on less than five instructions
-
o We must fetch more, issue less, and initiate execution on more than three instructions
Pregunta 96
Pregunta
132. Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
Respuesta
-
o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
-
o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
-
o The number of transistors switching will be proportional to the sustained rate
-
o The performance is proportional to the peak issue rate
Pregunta 97
Pregunta
131. Which of the written below is NOT increase power consumption?
Respuesta
-
o Increasing multithreading
-
o Increasing performance
-
o Increasing multiple cores
-
o Increasing multithreading(повторяется хз что тут )
Pregunta 98
Pregunta
130. Which of the following descriptions corresponds to dynamic power?
Respuesta
-
o Proportional to the product of the number of switching transistors and the switching rate
-
o Grows proportionally to the transistor count (whether or not the transistors are switching)
-
o Certainly a design concern
-
o None of the above
Pregunta 99
Pregunta
129. Which of the following descriptions corresponds to static power?
Respuesta
-
o Grows proportionally to the transistor count (whether or not the transistors are switching)
-
o Proportional to the product of the number of switching transistors and the switching rate Probability
-
o Proportional to the product of the number of switching transistors and the switching rate
-
o All of the above
Pregunta 100
Pregunta
128. (Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Respuesta
-
o Speedup
-
o Efficiency
-
o Probability
-
o Ration
Pregunta 101
Pregunta
127. A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Respuesta
-
• 90% 10%
-
o 70% 30%
-
o 50% 50%
-
o 89% 11%
Pregunta 102
Pregunta
126. What MTTF means:
Respuesta
-
o mean time to failure
-
o mean time to feauture
-
o mean this to failure
-
o my transfers to failure
Pregunta 103
Pregunta
125. Desktop benchmarks divide into __ broad classes:
Respuesta
-
o two
-
o three
-
o four
-
o five
Pregunta 104
Pregunta
124. Systems alternate between two states of service with respect to an SLA:
Respuesta
-
o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
-
o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
-
o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
-
o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
Pregunta 105
Pregunta
123. The most companies spend only ____________ of their income on R&D, which includes all engineering.
Respuesta
-
o 30% to 48%
-
o 4% to 12%
-
o 15% to 30%
-
o 1% to 17%
Pregunta 106
Pregunta
122. Volume is a ________ key factor in determining cost.
Respuesta
-
o second
-
o first
-
o fifth
-
o third
Pregunta 107
Pregunta
121. Manufacturing costs that decrease over time are ____
Respuesta
-
o the learning curve
-
o the cycled line
-
o the regular option
-
o the final loop
Pregunta 108
Pregunta
120. For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
Respuesta
-
o dynamic power
-
o physical energy
-
o constant supply
-
o simple battery
Pregunta 109
Pregunta
119. Integrated circuit processes are charecterized by the
Respuesta
-
o feature size
-
o permanent size n
-
o compex size
-
o fixed size
Pregunta 110
Pregunta
118. Products that are sold by multiple vendors in large volumes and are essentialy identical
Respuesta
-
o boxes
-
o files
-
o folders
-
o commodities
Pregunta 111
Pregunta
117. Learning curve itself is best measured by change in...
Respuesta
-
o bytes
-
o bits
-
o seconds
-
o yeld
Pregunta 112
Pregunta
116. Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Respuesta
-
o bandwidth
-
o throughput
-
o latency
-
o performance
Pregunta 113
Pregunta
115. The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Respuesta
-
o bandwidth
-
o latency
-
o throughput
-
o performance
Pregunta 114
Pregunta
1. Network performance depends of what?
Respuesta
-
o performance of swithes and transmission system
-
o performance of switches
-
o has no dependensies
-
o performance of transmission system
Pregunta 115
Pregunta
113. What is a “Kernel” in Cache Memory?
Respuesta
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution or waiting for synchronization variables
-
o Execution in user code
Pregunta 116
Pregunta
112. What is a “Synchronization” in Cache Memory?
Respuesta
-
o Execution in user code
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution or waiting for synchronization variables
Pregunta 117
Pregunta
111. What is a “Kernel” in Cache Memory?
Respuesta
-
o Execution or waiting for synchronization variables
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution in user code
Pregunta 118
Pregunta
110. What is a “Synchronization” in Cache Memory?
Respuesta
-
o Execution in the OS that is neither idle nor in synchronization access
-
o Execution in user code
-
o Execution or waiting for synchronization variables
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