13890952
Pregunta 1
Pregunta
Which of the following descriptions corresponds to static power?
Respuesta
-
Proportional to the product of the number of switching transistors and the switching rate
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Dominant energy consumer
-
All of the above
Pregunta 2
Pregunta
Which of the following descriptions corresponds to dynamic power?
Respuesta
-
Proportional to the product of the number of switching transistors and the switching rate
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Certainly a design concern
-
None of the above
Pregunta 3
Pregunta
Which of the written below is NOT increase power consumption?
Respuesta
-
Increasing performance
-
Increasing multiple cores
-
Increasing multithreading
-
Decreasing performance
Pregunta 4
Pregunta
Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when
Respuesta
-
The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
-
The number of transistors switching will be proportional to the sustained rate, and the performance is proportional to the peak issue rate
-
The number of transistors switching will be proportional to the sustained rate
-
The performance is proportional to the peak issue rate
Pregunta 5
Pregunta
How this process called: “Operations execute as soon as their operands are available”
Respuesta
-
data flow execution
-
instruction execution
-
data control execution
-
instruction field execution
Pregunta 6
Pregunta
If we want to sustain four instructions per clock
Respuesta
-
We must fetch less, issue more, and initiate execution on more than two instructions
-
We must fetch more, issue less, and initiate execution on more than three instructions
-
We must fetch more, issue more, and initiate execution on more than four instructions
-
We must fetch more, issue more, and initiate execution on less than five instructions
Pregunta 7
Pregunta
For what the reorder buffer is used :
Respuesta
-
To pass parameters through instructions that may be speculated
-
To pass results among instructions that may be speculated.
-
To get additional registers in the same way as the reservation stations
-
To control registers
Pregunta 8
Pregunta
How many fields contains the entry in the ROB:
Respuesta
-
5
-
6
-
3
-
4
Pregunta 9
Pregunta
Choose correct fields of entry in the ROB:
Respuesta
-
the source type, the destination field, the value field, and the ready field
-
the program type, the ready field, the parameter field, the destination field
-
the instruction type, the destination field, the value field, and the ready field
-
the instruction type, the destination field, and the ready field
Pregunta 10
Pregunta
Choose the steps of instruction execution:
Respuesta
-
issue, execute, write result, commit
-
execution, commit, rollback
-
issue, execute, override, exit
-
begin, write, interrupt, commit
Pregunta 11
Pregunta
Which Multiple-issue processors has not the hardware hazard detection:
Respuesta
-
Superscalar(dynamic)
-
Superscalar(static)
-
Superscalar(speculative)
-
EPIC
Pregunta 12
Pregunta
Examples of EPIC:
Respuesta
-
Pentium 4, MIPS R12K, IBM, Power5
-
Itanium
-
MIPS and ARM
-
TI C6x
Pregunta 13
Pregunta
Examples of superscalar(static):
Respuesta
-
Pentium 4, MIPS R12K, IBM, Power5
-
Itanium
-
MIPS and ARM
-
TI C6x
Pregunta 14
Pregunta
If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Respuesta
-
Static power
-
Dynamic power
-
Processing rate
-
Processor state
Pregunta 15
Pregunta
Examples of superscalar(dynamic) :
Respuesta
-
Pentium 4, MIPS R12K, IBM, Power5
-
None at the present
-
MIPS and ARM
-
TI C6x
Pregunta 16
Pregunta
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Respuesta
-
Static power
-
Dynamic power
-
Processing rate
-
Processor state
Pregunta 17
Pregunta
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Respuesta
-
Limited ILP due to software dependences
-
Achievable ILP with hardware resource constraints
-
Variability of ILP due to software and hardware interaction
-
Achievable ILP with software resource constraints
Pregunta 18
Pregunta
Examples of VLIW/LIW:
Respuesta
-
Pentium 4, MIPS R12K, IBM, Power5
-
Itanium
-
MIPS and ARM
-
TI C6x
Pregunta 19
Pregunta
What is a hash table?
Respuesta
-
Popular data structure for updating large collections, so that one can hardly answer questions
-
Popular tables for organizing a large collection of data structure
-
Popular data structure for organizing a large collection of data items so that one can quickly answer questions
-
Popular data structure for deleting small collections of data items so that one can hardly answer questions
Pregunta 20
Pregunta
A branch-prediction cache that stores the predicted address for the next instruction after a branch
Respuesta
-
branch-target buffer
-
data buffer
-
framebuffer
-
optical buffer
Pregunta 21
Pregunta
Buffering the actual target instructions allows us to perform an optimization which called:
Respuesta
-
branch folding
-
Branch prediction
-
Target instructions
-
Target address
Pregunta 22
Pregunta
Which of these is NOT characteristics of recent highperformance microprocessors?
Respuesta
-
Power
-
Functional unit capability
-
Clock rate
-
Color
Pregunta 23
Pregunta
Which is not the function of integrated instruction fetch unit:
Respuesta
-
Integrated branch prediction
-
Instruction prefetch
-
Instruction memory access and buffering
-
Instruction memory commit
Pregunta 24
Pregunta
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Respuesta
-
Address aliasing prediction
-
Branch prediction
-
Integrated branch prediction
-
Dynamic branch prediction
Pregunta 25
Pregunta
How to decrypt RISC?
Respuesta
-
Reduced Instruction Set Computer
-
Recall Instruction Sell Communication
-
Rename Instruction Sequence Corporation
-
Red Instruction Small Computer
Pregunta 26
Pregunta
The ideal pipeline CPI is a measure of …
Respuesta
-
the maximum performance attainable by the instruction
-
the minimum performance attainable by the implementation
-
the maximum performance attainable by the implementation
-
the minimum performance attainable by the instruction
Pregunta 27
Pregunta
what is the Pipeline CPI = ?
Respuesta
-
deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
-
deal pipeline CPU + Data hazard stalls + Control stalls
-
deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
-
Structural stalls + Data hazard stalls + Control stalls
Pregunta 28
Pregunta
The simplest and most common way to increase the ILP is …?
Respuesta
-
to exploit minimalism among iterations of a loop
-
to exploit parallelism among iterations of a loop
-
to destroy iterations of a loop
-
to decrease the minimalism of risk
Pregunta 29
Pregunta
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Respuesta
-
exploit-level parallelism
-
high-level minimalism
-
loop-level parallelism
-
low-level minimalism
Pregunta 30
Pregunta
In parallelism have three different types of dependences, tagging him:
Respuesta
-
data dependences , name dependences , and control dependences .
-
data dependences , name dependences , and surname dependences .
-
datagram dependences , name dependences , and animal dependences .
-
no correct answers
Pregunta 31
Pregunta
What is Name dependence?
Respuesta
-
name dependence occurs when two instructions use the same register or memory location
-
name dependence occurs when five or more instructions use the same register or memory location
-
name dependence occurs when instructions use the same name
-
All answers is correct
Pregunta 32
Pregunta
When occurs an output dependence?
Respuesta
-
when i and instruction j write the same name
-
when i and instruction j write the same register or memory location
-
when i and instruction j write the same adress or memory location
-
All answers is correct
Pregunta 33
Pregunta
What is RAW (read after write)?
Respuesta
-
when j tries to read a source before i writes it, so j incorrectly gets the old value
-
when i tries to read a source before j writes it, so j correctly gets the old value
-
when j tries to write a source before i writes it
-
when a tries to write a source before b read it, so a incorrectly gets the old value
Pregunta 34
Pregunta
What is given is not a hazard?
Respuesta
-
WAR
-
RAR
-
WAW
-
LOL
Pregunta 35
Pregunta
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Respuesta
-
loop-level
-
RAR
-
loop rolling
-
loop unrolling
Pregunta 36
Pregunta
Effect that results from instruction scheduling in large code segments is called…?
Respuesta
-
loop unrolling
-
loop-level
-
register pressure
-
registration
Pregunta 37
Pregunta
The simplest dynamic branch-prediction scheme is a
Respuesta
-
branch-prediction buffer
-
branch buffer
-
All answers correct
-
no correct answers
Pregunta 38
Pregunta
Branch predictors that use the behavior of other branches to make a prediction are called
Respuesta
-
correlating predictors or two-level predictors
-
branch-prediction buffer
-
branch table
-
three level loop
Pregunta 39
Pregunta
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Respuesta
-
the number of prediction entries selected by the branch = 1K.
-
the number of prediction entries selected by the branch = 2K.
-
the number of prediction entries selected by the branch = 8K.
-
the number of prediction entries selected by the branch = 4K.
Pregunta 40
Pregunta
What is the compulsory in Cs model?
Respuesta
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The number of accesses that miss divided by the number of accesses.
-
None of these
Pregunta 41
Pregunta
What is capacity in Cs model?
Respuesta
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
The number of accesses that miss divided by the number of accesses.
-
None of these
Pregunta 42
Pregunta
What is conflict in Cs model?
Respuesta
-
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
None of these
Pregunta 43
Pregunta
Choose the benefit of Cache Optimization.
Respuesta
-
Larger block size to reduce miss rate
-
Bigger caches to increase miss rat
-
Single level caches to reduce miss penalty
-
None of these
Pregunta 44
Pregunta
Choose the strategy of Seventh Optimization.
Respuesta
-
Critical word first
-
Critical restart
-
Sequential interleaving
-
Merging Write Buffer to Reduce Miss Penalty
Pregunta 45
Pregunta
Choose the Eight Optimization
Respuesta
-
Merging Write Buffer to Reduce Miss Penalty
-
Critical word first
-
Nonblocking Caches to Increase Cache Bandwidth
-
Trace Caches to Reduce Hit Time
Pregunta 46
Pregunta
Choose the Eleventh Optimization
Respuesta
-
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
-
Merging Write Buffer to Reduce Miss Penalty
-
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
-
None of these
Pregunta 47
Pregunta
What is the access time?
Respuesta
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
None of these
Pregunta 48
Pregunta
9. What is the cycle time?
Respuesta
-
The minimum time between requests to memory.
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of these
Pregunta 49
Pregunta
What does SRAM stands for?
Respuesta
-
Static Random Access memory
-
System Random Access memory
-
Short Random Access memory
-
None of these
Pregunta 50
Pregunta
What does DRAM stands for?
Respuesta
-
Dynamic Random Access memory
-
Dual Random Access memory
-
Dataram Random Access memory
-
None of these
Pregunta 51
Pregunta
What does DDR stands for?
Respuesta
-
Double data rate
-
Dual data rate
-
Double data reaction
-
None of these
Pregunta 52
Pregunta
What is kernel process?
Respuesta
-
Provide at least two modes, indicating whether the running process is a user process or an operating system process
-
Provide at least five modes, indicating whether the running process is a user process or an operating system process
-
Provide a portion of the processor state that a user process can use but not write
-
None of these
Pregunta 53
Pregunta
Which one is NOT concerning to pitfall?
Respuesta
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
Overemphasizing memory bandwidth in DRAMs
-
Predicting cache performance of one program from another
Pregunta 54
Pregunta
Which one is concerning to fallacy?
Respuesta
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
Predicting cache performance of one program from another
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
-
Overemphasizing memory bandwidth in DRAMs
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