17415950
Descripción
Test por хомяк убийца, actualizado hace más de 1 año
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Creado por хомяк убийца
hace más de 5 años
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Pregunta 1
Pregunta
Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:
Respuesta
-
a system clock
-
a system processor
-
a clock processor
-
a processor
-
a clock
Pregunta 2
Pregunta
Typically all operations performed by a processor begin with the:
Respuesta
-
pulse of the clock
-
pulse of the processor
-
it begins by itself
-
both of clock and processor pulse
-
none of the above
Pregunta 3
Pregunta
The time between pulses called?
Respuesta
-
clock speed
-
clock rate
-
cycle time
-
clock cycle
-
cycle rate
Pregunta 4
Pregunta
Typically, clock signals are generated by a ______, which generates a constant signal wave while power is applied.
Respuesta
-
quartz crystal
-
calcium crystal
-
zinc crystal
-
mercury crystal
-
radium crystal
Pregunta 5
Pregunta
A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:
Respuesta
-
Instruction execution rate
-
Instruction execution cycle
-
Instruction execution time
-
Instruction execution period
-
None of the above
Pregunta 6
Pregunta
Average cycles per instruction of a program called:
Respuesta
-
CPU
-
Clock cycle time
-
CPI
-
Clock rate
-
CPE
Pregunta 7
Pregunta
__ is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.
Respuesta
-
A benchmark suite
-
A performance suite
-
A IDE suite
-
A MIPS suite
-
None of the above
Pregunta 8
Pregunta
Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors
Respuesta
- True
- False
Pregunta 9
Pregunta
SPEC Benchmarks, which evaluates the performance of World Wide Web (WWW) servers:
Respuesta
-
SPECjvm98
-
SPECjbb2000
-
SPECweb99
-
SPECmail2001
-
all of the above
Pregunta 10
Pregunta
SPEC Benchmarks, which intended to evaluate performance of the combined hardware and software aspects of the Java Virtual Machine (JVM) client platform:
Respuesta
-
SPECjvm98
-
SPECjbb2000
-
SPECweb99
-
SPECmail2001
-
all of the above
Pregunta 11
Pregunta
SPEC Benchmarks, which for evaluating server-side Java-based electronic commerce applications:
Respuesta
-
SPECjvm98
-
SPECjbb2000
-
SPECweb99
-
SPECmail2001
-
all of the above
Pregunta 12
Pregunta
SPEC Benchmarks, which designed to measure a system’s performance acting as a mail server
Respuesta
-
SPECjvm98
-
SPECjbb2000
-
SPECweb99
-
SPECmail2001
-
all of the above
Pregunta 13
Pregunta
ENIAC stands for:
Respuesta
-
Electronic Numerical Integrator and Computer
-
Electronic Nuclear Integrator and Computer
-
Encapsulation Numerical Integrator and Commerce
-
Encapsulation Numerical Integrator and Computer
-
Electronic Numerical Integer and Computer
Pregunta 14
Pregunta
The general structure of the IAS computer:
Respuesta
-
main memory
-
arithmetic and logic unit
-
control unit
-
Input/output equipment
-
all of the above
Pregunta 15
Pregunta
Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
Respuesta
-
Memory buffer register (MBR)
-
Memory address register (MAR)
-
Instruction register (IR)
-
Instruction buffer register (IBR)
-
Program counter (PC)
Pregunta 16
Pregunta
Specifies the address in memory of the word to be written from or read into the MBR
Respuesta
-
Memory buffer register (MBR)
-
Memory address register (MAR)
-
Instruction register (IR)
-
Instruction buffer register (IBR)
-
Program counter (PC)
Pregunta 17
Pregunta
Contains the 8-bit opcode instruction being executed.
Respuesta
-
Memory buffer register (MBR)
-
Memory address register (MAR)
-
Instruction register (IR)
-
Instruction buffer register (IBR)
-
Program counter (PC)
Pregunta 18
Pregunta
Employed to hold temporarily the right-hand instruction from a word in memory
Respuesta
-
Memory buffer register (MBR)
-
Memory address register (MAR)
-
Instruction register (IR)
-
Instruction buffer register (IBR)
-
Program counter (PC)
Pregunta 19
Pregunta
Contains the address of the next instruction pair to be fetched from memory.
Respuesta
-
Memory buffer register (MBR)
-
Memory address register (MAR)
-
Instruction register (IR)
-
Instruction buffer register (IBR)
-
Program counter (PC)
Pregunta 20
Pregunta
Transistor is a solid-state device, made from silicon
Respuesta
- True
- False
Pregunta 21
Pregunta
The use of the _______ defines the second generation of computers.
Respuesta
-
Vacuum tube
-
Transistor
-
Small- and medium-scale integration
-
Large-scale integration
-
Very-large-scale integration
Pregunta 22
Pregunta
The use of the _______ defines the first generation of computers.
Respuesta
-
Vacuum tube
-
Transistor
-
Small- and medium-scale integration
-
Large-scale integration
-
Very-large-scale integration
Pregunta 23
Pregunta
The use of the ________ defines the third generation of computers.
Respuesta
-
Vacuum tube
-
Transistor
-
Small- and medium-scale integration
-
Large-scale integration
-
Very-large-scale integration
Pregunta 24
Pregunta
The use of the _________ defines the fourth generation of computers.
Respuesta
-
Vacuum tube
-
Transistor
-
Small- and medium-scale integration
-
Large-scale integration
-
Very-large-scale integration
Pregunta 25
Pregunta
The use of the _________ defines the fifth generation of computers.
Respuesta
-
Vacuum tube
-
Transistor
-
Small- and medium-scale integration
-
Large-scale integration
-
Very-large-scale integration
Pregunta 26
Pregunta
Moore’s law: “The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic
Respuesta
- True
- False
Pregunta 27
Pregunta
Moore’s law: “Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed”
Respuesta
- True
- False
Pregunta 28
Pregunta
Moore’s law: “The computer becomes smaller, making it more convenient to place in a variety of environments”
Respuesta
- True
- False
Pregunta 29
Pregunta
Moore’s law: “There is a reduction in power and cooling requirements”
Respuesta
- True
- False
Pregunta 30
Pregunta
Moore’s law: “The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections”
Respuesta
- True
- False
Pregunta 31
Pregunta
When Intel was developed its 4004, it is the first chip to contain all of the components of a CPU on a single chip, later known as Microprocessor
Respuesta
-
1973
-
1971
-
1972
-
1974
-
1970
Pregunta 32
Pregunta
Processor can simultaneously work on multiple instructions. How this technique called?
Respuesta
-
Branch prediction
-
Pipelining
-
Data flow analysis
-
Speculative execution
-
None of the above
Pregunta 33
Pregunta
The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next
Respuesta
-
Branch prediction
-
Pipelining
-
Data flow analysis
-
Speculative execution
-
None of the above
Pregunta 34
Pregunta
The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
Respuesta
-
Branch prediction
-
Pipelining
-
Data flow analysis
-
Speculative execution
-
None of the above
Pregunta 35
Pregunta
This enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed
Respuesta
-
Branch prediction
-
Pipelining
-
Data flow analysis
-
None of the above
-
Speculative execution
Pregunta 36
Pregunta
The “natural” unit of organization of memory
Respuesta
-
Word
-
Addressable units
-
Unit of transfer
-
Sequential access
-
Direct access
Pregunta 37
Pregunta
For main memory, this is the number of bits read out of or written into memory at a time
Respuesta
-
Word
-
Addressable units
-
Unit of transfer
-
Sequential access
-
Direct access
Pregunta 38
Pregunta
Memory is organized into units of data, called records; access must be made in a specific linear sequence
Respuesta
-
Word
-
Addressable units
-
Unit of transfer
-
Sequential access
-
Direct access
Pregunta 39
Pregunta
For random-access memory, this is the time it takes to perform a read or write operation
Respuesta
-
Access time
-
Memory cycle time
-
Transfer rate
-
Performance
-
All of the above
Pregunta 40
Pregunta
The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
Respuesta
- True
- False
Pregunta 41
Pregunta
The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
Respuesta
- True
- False
Pregunta 42
Pregunta
Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches
Respuesta
-
Bus watching with write through
-
Hardware transparency
-
Noncacheable memory
-
Software transparency
-
None of the above
Pregunta 43
Pregunta
Each cache controller monitors the address lines to detect write operations to memory by other bus masters
Respuesta
-
Bus watching with write through
-
Hardware transparency
-
Noncacheable memory
-
Software transparency
-
None of the above
Pregunta 44
Pregunta
Only a portion of main memory is shared by more than one processor, and this is designated as:
Respuesta
-
Bus watching with write through
-
Hardware transparency
-
Noncacheable memory
-
Software transparency
-
None of the above
Pregunta 45
Pregunta
Larger blocks increase the number of blocks that fit into a cache; because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched
Respuesta
- True
- False
Pregunta 46
Pregunta
A state in which data requested for processing by a component or application is found in the cache memory
Respuesta
-
cache hit
-
cache miss
-
cache overwrites
-
cache set
-
cache access time
Pregunta 47
Pregunta
The basic element of a semiconductor memory is:
Respuesta
-
memory cell
-
cache memory
-
RAM
-
DRAM
-
None of the above
Pregunta 48
Pregunta
RAID stands for
Respuesta
-
Random Access Integral Disk
-
Redundant Access Integral Disk
-
Random Array Independent Disk
-
Redundant Array Independent Disk
-
Redundant Access Independent Disk
Pregunta 49
Pregunta
Data are recorded on and later retrieved from the disk via a conducting coil named the tail
Respuesta
- True
- False
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