17514397
Descripción
Test por хомяк убийца, actualizado hace más de 1 año
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Creado por хомяк убийца
hace más de 5 años
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Pregunta 1
Pregunta
The main computer that stores the files that can be sent to computers that are
networked together is...?:
Respuesta
-
Clip art
-
Mother board
-
Peripheral
-
File server
Pregunta 2
Pregunta
Addressing mode used in instruction: add r1, r2, r3 is?
Respuesta
-
Register
-
Indirect
-
Base
-
Immediate
Pregunta 3
Pregunta
In generic microprocessor instruction time is…?
Respuesta
-
Exactly same as machine cycle time
-
Shorter than machine cycle time
-
Larger than machine cycle time
-
Ten times machine cycle time
Pregunta 4
Pregunta
Hardware devices that are not part of the main computer system and are often added later to the system?
Respuesta
-
Peripheral
-
Clip art
-
Highlight
-
Execute
Pregunta 5
Pregunta
Using a(n) _____ protocol, the sender and the receiver are synchronized by a
signal called a clock
Respuesta
-
synchronous
-
asynchronous
-
analogue
-
block
Pregunta 6
Pregunta
The bandwidth of a(n) _____ signal is usually measured in bits per second.
Respuesta
-
video
-
digital
-
satellite
-
analog
Pregunta 7
Pregunta
A communications _____ is a physical path or frequency for a signal
transmission.
Respuesta
-
band
-
channel
-
protocol
-
bridge
Pregunta 8
Pregunta
Which of the following terms represents the transmission capacity of a
communications channel?
Respuesta
-
Indexing
-
Frequency
-
Bandwidth
-
Resolution
Pregunta 9
Pregunta
How many parts of Memory Hierarchy?
Respuesta
-
5
-
4
-
2
-
3
Pregunta 10
Pregunta
In Memory Hierarchy, at the Outboard storage which of the following are
included:
Respuesta
-
Cache
-
Main memory
-
Magnetic tape
-
Magnetic disk
Pregunta 11
Pregunta
In Memory Hierarchy, at the Off-line storage which of the following are included:
Respuesta
-
Cache
-
Magnetic disk
-
Magnetic tape
-
Main memory
Pregunta 12
Pregunta
In Memory Hierarchy, at the Inboard memory which of the following are
included:
Respuesta
-
Main memory
-
Magnetic disk
-
Magnetic tape
-
Optical disk
Pregunta 13
Pregunta
Cache Design has these properties?
Respuesta
-
Size, block size, mapping function, replacement algorithm, write policy
-
Size, search function, write function, read policy, vector algorithm
-
Size, mapping algorithm, vector function, write policy, replacement function
-
Size, blocking algorithm, search function, replacement vector, read policy
Pregunta 14
Pregunta
Three techniques are possible for I/O operations:
Respuesta
-
Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
-
Object-oriented I/O, Design I/O, Usable I/O
-
Machine I/O, Architecture I/O, Hardware I/O
-
Control I/O, Status I/O, Transfer I/O
Pregunta 15
Pregunta
How many principles has Deadlock?
Respuesta
-
3
-
5
-
2
-
6
Pregunta 16
Pregunta
Which of the following principles has Deadlock?
Respuesta
-
Prevention, Avoidance, Detection
-
Execution, Association, Starvation
-
Exclusion, Avoidance, Starvation
-
Starvation, Detection, Exclusion
Pregunta 17
Pregunta
Much of the work in security and protection as it relates to operating systems
can be roughly grouped into four categories?
Respuesta
-
Availability, confidentiality, data integrity, authenticity
-
Safety, accountability, reliability, density
-
Usability, integrity, confidentiality, reliability
-
Flexibility, availability, accountability, authenticity
Pregunta 18
Pregunta
The central themes of operating system design are all concerned with the
management of processes and threads?
Respuesta
-
Multiprogramming, multiprocessing, distributed processing
-
Multitasking, multiprogramming, multithreading
-
Multiprocessing, uniprocessing, multitasking
-
Multithreading, distributed processing, uniprocessing
Pregunta 19
Pregunta
Can you solve the Dining Philosophers’ Problem using monitors?
Respuesta
-
yes
-
no
Pregunta 20
Pregunta
Assembly line operation is also called as?
Respuesta
-
Superscalar operation
-
pipelining process
-
Von-Neumann cycle
-
None of the mentioned
Pregunta 21
Pregunta
The CISC stands for?
Respuesta
-
Computer Instruction Set Compliment
-
Complete Instruction Set Compliment
-
Computer Indexed Set Components
-
Complex Instruction Set Computer
Pregunta 22
Pregunta
The secondary effect that results from instruction scheduling in large code
segments is called ____?
Respuesta
-
Aggressive instruction
-
Correlating predictors
-
Register predictors
-
Register pressure
Pregunta 23
Pregunta
How many instructions can be implemented in MIPS?
Respuesta
-
2 clock cycles
-
3 clock cycles
-
4 clock cycles
-
5 clock cycles
Pregunta 24
Pregunta
What do you call the given statement as: “The number successful accesses to
memory stated as a fraction.”
Respuesta
-
Hit rate
-
Miss rate
-
Success rate
-
Access rate5 clock cycles
Pregunta 25
Pregunta
Of the following, identify the memory usually written by the manufacturer.
Respuesta
-
RAM
-
DRAM
-
ROM
-
Cache memory
Pregunta 26
Pregunta
The Sun micro systems processors usually follow _____ architecture
Respuesta
-
CISC
-
ISA
-
ULTRA SPARC
-
RISC
Pregunta 27
Pregunta
The iconic feature of the RISC machine among the following are
Respuesta
-
Reduced number of addressing modes
-
Increased memory size
-
Having a branch delay slot
-
All of the above
Pregunta 28
Pregunta
Pipe-lining is a unique feature of _
Respuesta
-
RISC
-
СISC
-
IANA
-
ISA
Pregunta 29
Pregunta
Performance of a machine is determined by:
Respuesta
-
Instruction count, Clock cycle time, Clock cycles per instruction
-
Instruction count, Clock cycle time, Correlating predictors
-
Clock cycle time, Correlating predictors, Aggressive instruction
-
Clock cycle time, Clock cycles per instruction, Correlating predictors
Pregunta 30
Pregunta
What do you call the given statement as for type of memory?: “High density, low
power, cheap, slow, need to be “refreshed” regularly”
Respuesta
-
DRAM
-
SRAM
-
CISC
-
RAM
-
ROM
Pregunta 31
Pregunta
Definition of Block:
Respuesta
-
minimum unit that is present or not present
-
location of block in memory
-
percentage of time item not found in upper level
-
memory closer to processor
-
time to access upper level
Pregunta 32
Pregunta
Definition of Block address:
Respuesta
-
minimum unit that is present or not present
-
location of block in memory
-
percentage of time item not found in upper level
-
memory closer to processor
-
time to access upper level
Pregunta 33
Respuesta
-
196
-
784
-
512
-
1024
Pregunta 34
Pregunta
What is the total number of writes that miss in the cache?
Respuesta
-
588
-
196
-
25%
-
12,5%
Pregunta 35
Pregunta
What is the total number of writes that hit in the cache?
Respuesta
-
588
-
784
-
12,5%
Pregunta 36
Pregunta
Suppose that we want to enhance the processor used for Web serving. The new
processor is 10 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Respuesta
-
≈ 1.86
-
≈ 1.96
-
≈ 1.56
-
1.30
Pregunta 37
Pregunta
Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Respuesta
-
≈ 1.25
-
≈ 1.96
-
≈ 1.56
-
1.30
Pregunta 38
Pregunta
Suppose that we want to enhance the processor used for Web serving. The new
processor is 5 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 50% of the time and is waiting for I/O 50% of the time, what is the
overall speedup gained by incorporating the enhancement?
Respuesta
-
≈ 1.86
-
≈ 1.96
-
≈ 1,67
-
1.30
Pregunta 39
Pregunta
Suppose that we want to enhance the processor used for Web serving. The new
processor is 2 times faster on computation in the Web serving application than
the original processor. Assuming that the original processor is busy with
computation 30% of the time and is waiting for I/O 70% of the time, what is the overall speedup gained by incorporating the enhancement?
Respuesta
-
≈ 1.86
-
≈ 1.18
-
≈ 1.56
Pregunta 40
Pregunta
What is a RISC?
Respuesta
-
Reduced Instruction Set Computer
-
Rational Interruptible Security Computer
-
Research Interconnect Several Computer
Pregunta 41
Pregunta
When single-processor performance improvement has dropped?
Respuesta
-
2003
-
2004
-
2002
Pregunta 42
Pregunta
How much in percentage single-processor performance improvement has dropped to less than?
Respuesta
-
22
-
11
-
33
Pregunta 43
Pregunta
What is the RLP?
Respuesta
-
Research Level Parallelism
-
Random Level Parallelism
-
Request Level Parallelism
Pregunta 44
Pregunta
How many classes of computers classified?
Respuesta
-
7
-
3
-
5
Pregunta 45
Pregunta
Which distance of price has Clusters/warehouse-scale computers?
Respuesta
-
100 000 - 200 000 000 $
-
5 000 – 10 000 000 $
-
100 – 100 000 $
Pregunta 46
Pregunta
What is the PMD in computer classes?
Respuesta
-
Percentage map device
-
Powerful markup distance
-
Peak maze development
-
Personal mobile device
Pregunta 47
Pregunta
The Application of Brokerage operations how many cost of downtime per hour?
Respuesta
-
8 870 000 $
-
6 450 000 $
-
7 550 000 $
Pregunta 48
Pregunta
What is the Vector Architectures and Graphic Processor Units (GPUs) -
Respuesta
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Pregunta 49
Pregunta
What is the Thread Level Parallelism -
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Pregunta 50
Pregunta
What is the Request Level Parallelism:
Respuesta
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Pregunta 51
Pregunta
What is the Instruction Level Parallelism:
Respuesta
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Pregunta 52
Pregunta
What is the MISD one of the categories of computers?
Respuesta
-
Multiple Instructions Streams, Single Data Stream
-
Multiple Instruction Streams, Multiple Data Streams
-
Multiple Instruction Streams, Set Data Stream
Pregunta 53
Pregunta
How many elements in Trends of Technology?
Respuesta
-
3
-
4
-
5
Pregunta 54
Pregunta
How many elements of the Instruction Set Architecture (ISA):
Respuesta
-
5
-
6
-
7
Pregunta 55
Pregunta
What is a ARF:
Respuesta
-
Architectural Register File
-
Architecture Relocation File
-
Architecture Reload File
-
Architectural Read File
Pregunta 56
Pregunta
What is a ROB?
Respuesta
-
Reorder Buffer
-
Read Only Buffer
-
Reload Buffer
-
Recall Buffer
Pregunta 57
Pregunta
What is a FSB?
Respuesta
-
Finished Store Buffer
-
Finished Stack Buffer
-
Finished Stall Buffer
-
Finished Star Buffer
Pregunta 58
Pregunta
What is a PRF?
Respuesta
-
Physical Register File
-
Pending Register File
-
Pipeline Register File
-
Pure Register File
Pregunta 59
Pregunta
What is a SB?
Respuesta
-
Scoreboard
-
Scorebased
-
Scaleboard
-
Scalebit
Pregunta 60
Pregunta
How many stages used in Superscalar (Pipeline)?
Respuesta
-
5
-
4
-
6
Pregunta 61
Pregunta
What is about Superscalar means “F-D-X-M-W”?
Respuesta
-
Fetch, Decode, Execute, Memory, Writeback
-
Fetch, Decode, Instruct, Map, Write
-
Fetch, Decode, Excite, Memory, Write
-
Fetch, Decode, Except, Map, Writeback
Pregunta 62
Pregunta
Speculating on Exceptions “Prediction mechanism” is -
Respuesta
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
none
Pregunta 63
Pregunta
Speculating on Exceptions “Check prediction mechanism” is -
Respuesta
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
The way in which an object is accessed by a subject
-
none
Pregunta 64
Pregunta
Speculating on Exceptions “Recovery mechanism” is -
Respuesta
-
Only write architectural state at commit point, so can throw away partially executed instructions after exception
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
An entity capable of accessing objects
-
none
Pregunta 65
Pregunta
What is a RT?
Respuesta
-
Rename Table
-
Recall Table
-
Relocate Table
-
Remove Table
Pregunta 66
Pregunta
What is a FL?
Respuesta
-
Free List
-
Free Last
-
Free Leg
-
Free Launch
Pregunta 67
Pregunta
What is an IQ?
Respuesta
-
Issue Queue
-
Internal Queue
-
Interrupt Queue
-
Instruction Queue
Pregunta 68
Pregunta
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Respuesta
-
Width and Lifetime
-
Width and Height
-
Time and Cycle
-
Length and Addition
Pregunta 69
Pregunta
Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?
Respuesta
-
Register name
-
Instruction cache
-
Data tags
-
Data cache
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