computer architecture acronyms

Pregunta	Respuesta
ALU	ARITHMETIC LOGIC UNIT
ENIAC	ELECTRONIC NUMERICAL INTEGRATOR AND COMPUTER
EDVAC	ELECTRONIC DISCRETE VARIABLE AUTOMATIC COMPUTER
CPU	CENTRAL PROCESSSING UNIT
GUI	GRAPHICAL USER INTERFACE
FPGA	FIELD PROGRAMMABLE GATE ARRAY
PDA	PERSONAL DIGITAL ASSISTANT
RFID	RADIO FREQUENCY IDENTIFICATION
COTS	COMMODITY OFF THE SHELF
MMX	MULTIMEDIA EXTENTIONS
SIMD	SINGLE INSTRUCTION MULTIPLE DATA
MIMD	MULTIPLE INSTRUCTION MULTIPLE DATA
ASCII	AMERICAN StANDARD CODE INFORMTAION INTERCHANGE
EDSAC	ELECTRONIC DELAY STORACE AUTOMATIC CALCULATOR
SSE	Streaming SIMD Extensions
PC	PROGRAM COUNTER
IR	INSTRUCTION REGISTER
RISC	REDUCED INSTARUCTION SET COMPUTING
CISC	COMPLEX INSTRUCTION SET COMPUTING
MIPS	MILLIONS OF INSTRUCTIONS PER SECONDS
BCD	BINARY CODED DECIMAL
SIMM	SINGLE INLINE MEMORY MODULE
DIMM	DUAL INLINE MEMORY MODULE
SO-DIMM	SMALL OUTLINE DUAL INLINE MEMORY MODULE
BIOS	BASIC INPUT OUTPUT SYSTEMS
IDE	INTERGRATED DRIVE ELECTRONICS
LBA	LOGICAL BLOCK ADDRESSING
SCSI	SMALL COMPUTER SYSTEM INTERFACE
RAID	REDUNDANT ARRAY INDEPENDENT DISK
SLED	SMALL LARGE EXPENSIVE DISK
SSD	SOLID STATE DRIVE
CD-ROM	COMPACT DISK READ ONLY MEMORY
CD-RW	COMPACT DISK REWRITABLE
DVD	DIGITAL VERSERTILE DISK
DMA	DIGITAL MEMORY ADDRESS
ISA	INSTRUCION SET ARCHITECTURE
EISA	EXTENDED INSTRUCTION SET ARCHITECTURE
PCI	PERIPHERAL COMPONENT INTERCONNECT
PCIe	PERIPHERAL COMPONENT INTERCONNECT EXPRESS
CRT	CATHODE RAY TUBE
LCD	LIQUID CRYSTAL DISPLAY
OLED	ORGANIC LIGHT EMITTING DIODE
IC	INTERGRATED CUIRCUITS
DIP	DUAL IN-LINE PACKAGE
PGA	PIN GRID ARRAY
LGA	LAND GRID ARRAY
RAM	RANDOM ACCESS MEMORY
SRAM	STATIC RANDOM ACCESS MEMORY
DRAM	DYNAMIC RANDOM ACCESS MEMORY
SDRAM	SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY
DDR	DOUBLE DATA RATE
FPM	FAST PAGE MODE
EDO	EXTENDED DATA OUTPUT
PROM	PROGRAMMABLE READ ONLY MEMORY
EPROM	ERASABLE PROGRAMMABLE READ ONLY MEMORY
EEPROM	ELECTRICAL ERASABLE PROGRAMMABLE READ ONLY MEMORY
LUT	LOOK UP TABLE
APIC	ADVANCED PROGRAMMABLE INTERUPT CONTROLLER
USB	UNIVERSAL SERIAL BUS
CRC	CYCLIC REDUNDANCY CHECK
PIO	PARALLEL INPUT OUTPUT
MAR	MEMORY ACCESS REGISTER
MDR	MEMORY DATA REGISTER
MPC	MICRO PROGRAM COUNTER
MIR	MICRO INSTRUCTION REGISTER
FSM	FINITE STATE MACHINE
LRU	LEAST RECENTLY USED
IBM	INTERNATIONAL BUSINESS MACHINES
DEC	DIGITAL EQUIPTMENT CORPORATION
IFU	INSTRUCTION FETCH UNIT
BTB	BRANCH TARGET BUFFER
TLB	TRANSITION LOOKASIDE BUFFER
CLB	CONFIGURABLE LOGIC BLOCK
IOB	INPUT OUTPUT BLOCK

Siguiente

Descripción

Resumen del Recurso

Similar

	Creado por Tolu Awosanya hace casi 9 años