12206892
Descripción
Mapa Mental por Lim Wei Hong, actualizado hace más de 1 año
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Creado por Lim Wei Hong
hace casi 7 años
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Chapter 7 Pipelining & RISC
- Pipelining strategy
- Pipelining
- Two-stage Instruction Pipeline
- Additional stages
- Fetch instruction
- Decode instruction
- Calculate operands
- Fetch operands
- Execute instruction
- Write operand
- Fetch instruction
- Two-stage Instruction Pipeline
- Pipelining of unequal stages
- Pipelining
- Pipeline Hazards
- Type of data hazard
- Read After Write (RAW)
- Write After Read (WAR)
- Write After Write (WAW)
- Read After Write (RAW)
- Control Hazard
- Type of data hazard
- Reduced Instruction Set Computers (RISC)
- Characteristics of RISC
- One machine instruction per machine cycle
- Register-to-register
- Simple Addressing modes
- Simple instruction formats
- One machine instruction per machine cycle
- CISC versus RISC characteristics
- Quantitative
- Qualitative
- Have high differences during comparisons
- Quantitative
- Characteristics of RISC
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