Storage Systems, “Higher associativity to reduce miss rate”
The simplest way to reduce the miss rate to take advantage of spatial locality and increase the block size
The obvious way to reduce capacity misses is to increase cache capacity
Obviously, increasing associativity reduces conflict misses
How many Optimizations’ in Cache memory Performance?
6
8
10
Storage Systems, “Larger block size to reduce miss rate”
What is the “Read Operands” in simple five-stage pipeline?
Wait until no data hazards, then reads the operand
Decode instructions, check for structural hazards
Storage Systems, “Bigger caches to reduce miss rate”
Tenth optimization of Cache Memory “Register prefetch”?
Loads data only into the cache and not the register
Will load the value into register
At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”?
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Faults in software (usually) and hardware design (occasionally)
Mistakes by operations and maintenance personnel
What is a “Kernel” in Cache Memory?
Execution or waiting for synchronization variables
Execution in user code
Execution in the OS that is neither idle nor in synchronization access
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Average time per task in the queue
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
How many steps took Virtual Machine Monitor to improve performance of virtual machines?
5
3
4
How many issue queue used in Centralized Superscalar 2 and Exceptions
2
1
Which of the following formula is true about Issue Queue for “Instruction Ready”
Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
What is the “Read Operands” in Pipelining Basics?
Wait until no control hazards, then reads the operand
Wait until no structural hazards, then reads the operand
Perfect caches at The Hardware Model?
All memory accesses take one clock cycle
All conditional branches are predicted exactly
All memory addresses are known exactly
How many stages used in Superscalar (Pipeline)?
7
How much in percentage single-processor performance improvement has dropped to less than?
22%
33%
11%
What is “VLIW”?
Very Long Instruction Word
Very Less Interpreter Word
Very Light Internal Word
Very Low Invalid Word
At VLIW by “performance and loop iteration” which time is shorter?
Software Pipelined
Loop Unrolled
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
What single-processor performance improvement has dropped?
2004
2002
2003
What does MAF?
Miss Address File
Map Address File
Memory Address File
How many classes of computers classified?
Sixth Optimization of Cache Memory “Critical word first”?
Fetch the words in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
Request the missed word first from memory and send it to the processor as soon as it arrives, let the processor continue execution while filling the rest of the words in the block
In an important early study of intrusion, Anderson[ANDE80] identified three classes of intruders:
Control, exploit, system
Masquerader, misfeasor, clandestine user
Individual, legitimate, authorized
Outside, inside, offside
How many elements of the Instruction Set Architecture (ISA):
What is the “Bigger caches to reduce miss rate” at Basics of Memory Hierarchies
At storage systems Gray and Siewiorek classify faults what does mean “Design faults”?
What is the ARF?
Architectural Register File
Architecture Relocation File
Architecture Reload File
Architectural Read File
What is the Conflict in main categories in Cache Memory?
first-reference to a block, occur even with infinite cache
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is?
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
CPU time-Cache Miss-Miss Penalty-CPU time
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Width and Lifetime
Width and Height
Time and Cycle
Length and Addition
What is a “Synchronization” in Cache Memory?
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is?
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Flash memory is a type of?
Electronically Erasable Programmable Read-Only Memory
Electronically Extensible Programmable Re-Order Memory
Electronically Executable Programmable Reduce Memory
Access time at memory latency is -
The time between when a read is requested and when the desired word arrives
The minimum time between unrelated requests to memory
In Multilevel Caches “Local miss rate” equals =
misses in cache / accesses to cache
misses in cache / CPU memory accesses
misses in cache / number of instructions
What is a RAID 1?
Also called mirroring or shadowing, there are two copies of every piece of data
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
This organization was inspired by applying memory-style error correcting codes to disks
RAW (read after write)?
This hazard corresponds to an output dependence
This hazard is the most common type and corresponds to a true data dependence
This hazard arises n antidependence (or name dependence)
How many size of Cache L3 is true approximately?
3 MB
256 MB
256 KB
What is a RAID 3?
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
Many applications are dominated by small accesses
What is the increasing cache bandwidth?
Critical word first and merging write buffer
Pipelined caches, multibanked caches and non-blocking caches
Small and simple first-level caches and way-prediction
What is RAID 2?
In Non-Blocking Caches what does mean “Critical word first”?
Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
Sixth optimization of cache memory “Early restart”?
Fetch the word in normal order, but as soon as the requested word of the block arrives send it to the processor and let the processor continue execution
How many size of Cache L2 is true approximately?
4 KB
32 MB
Reducing the miss penalty or miss rate via parallelism?
Hardware prefetching and compiler prefetching
Compiler optimization
What is a RT?
Rename Table
Recall Table
Relocate Table
Remove Table
How many functions at integrated instruction fetch units?
What is the PMD in computer classes?
Percentage map device
Personal mobile device
Powerful markup distance
Peak maze development
The second type of dependence is?
Data dependence
Name dependence
Control dependence
How many elements presented at performance trends: bandwidth over latency?
What is the compulsory in main categories in cache memory?
Cache is too small to hold all data needed by program, occur even under perfect replacement policy(loop over 5 cache lines)
Misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
First-reference to a block, occurs even with infinite cache
How many elements in trends of technology?
Perfect memory address alias analysis at the Hardware model?
Speculating on exceptions “Recovery mechanism” is –
Exceptions are rare, so simply predicting no exceptions is very accurate
Only write architectural state at commit point, so can throw away partially executed instructions after exception
None of them
An entity capable of accessing objects
What is the reducing the miss rate?
Performance optimization
Time optimization
DDR is –
Double data rate
Density data rate
Dynamic data rate
In Non-blocking caches what does mean “Early restart”?
Which distance of price has clusters/warehouse-scale computers?
100-100 000$
100 000-200 000 000$
5 000 -10 000 000$
Little’s Law and a series of definitions lead to several useful equations for “Time System”-
What is the MISD one of the categories of computers?
Multiple instructions streams, set data stream
Multiple instructions streams, single data stream
Multiple instruction stream, multiple data streams
What is a RAID 4?
Tenth Optimization of cache memory “Cache prefetch”?
Will load the value into a register
What is the Request level parallelism?
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
Exploits parallelism among largely decoupled tasks specified by the programmer or the operating system
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Non-blocking cache timeline for “Hit under miss” the sequence is -?
At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”?
WAR(write after read)?
This hazard correspond to an output dependence
This hazard arises from an antidependence (or name dependence)
Main term of dependability is SLAs?
Scale level approach
Service level agreements
Standard level achievement
At VLIW by “performance and loop iteration” which time is longer?
Loop unrolled
What is the temporal locality?
Exploit by remembering the contents of recently accessed locations
Exploit by fetching blocks of data around recently accessed locations
What is an IQ?
Issue Queue
Internal Queue
Interrupt Queue
Instruction Queue
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time”-?
The time between when the user enters the command and the complete response is displayed
The time for the user to enter the command
The time from the reception of the response until the user begins to enter the next command
How many size of Cache L1 is true approximately?
8 KB
2 MB
What is a RISC computers?
Reduced instruction set computer
Research interconnect several computer
Rational interruptible security computer
The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
What is the “opcode”?
Operand code
Optional code
Operation code
WAW(write after write)?
What is the Vector Architectures and graphic processor units(GPUs)?
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
Speculating on exceptions “Check prediction mechanism” is –
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
The way in which an object is accessed by a subject
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Speculative operations that don’t cause exceptions
Hardware to check pointer hazards
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion:
What is PRF?
Pipeline Register File
Physical Register File
Pure Register File
Pending Register File
Speculation and the Challenge of Energy efficiency consume excess energy in how many ways?
How many instructions used in Distributed Superscalar 2 and Exceptions?
What is about Superscalar means “F-D-X-M-W”?
Fetch, Decode, Instruct, Map, Write
Fetch, Decode, Excite, Memory, Write
Fetch, Decode, Except, Map, Writeback
Fetch, Decode, Execute, Memory, Writeback
SDRAM is -
Synchronous dynamic random access memory
Static dynamic random access memory
Super dynamic random access memory
How many restrictions RAW hazards through memory are maintained?
In Multilevel Caches “Misses per instruction” equals =
Misses in cache / number of instructions
Misses in cache / accesses to cache
Misses in cache / CPU memory accesses
How many possible Elements of Data Hazards?
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” ?
Clock cycle time is -
Hardware technology and organization
Organization and instruction set architecture
Instruction set architecture and compiler technology
A virus classification by target includes the following categories. What is a File infector?
The key is stored with the virus
Far more sophisticated techniques are possible
A typical approach is as follows
Infects files that the operating system or shell consider to be executable
What is an ALAT?
Addition Long Accessibility Table
Allocated Link Address Table
Allowing List Address Table
Advanced Load Address Table
CPI is -
What is SB?
Scaleboard
Scoreboard
Scorebased
Scalebit
At Critical Word First for miss penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
0,1,2,3,4,5,6,7
3,4,5,6,7,0,1,2
At Critical Word First for miss penalty chose correct sequence of Blocking Cache with critical word first “Order of fill”:
What is a RAID 0?
This organization was inspired by applying memory-style errorcorrecting codes to disks
it has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks”, although the data may be striped across the disks in the array
What is a file?
It is the basic element of data
it is a collection of related fields that can be treated as a unit by some application program
it is a collection of related data
it is a collection of similar records
What is the reducing the miss penalty?
Pipelined caches, multibanked caches, and nonblocking caches
Little’s Law and a series of definitions lead to several useful equations for “length server”-:
Average length of queue
Average number of tasks in service
At storage systems gray and Siewiorek classify faults what does mean “environmental faults”?
Fire, flood, earthquake, power failure and sabotage
How many types of dependencies do you know?
How many major flavors in multiple-issue processors?
Out-of-order control complexity MIPS R10000 which is not in control logic?
CLK
Address queue
Integer datapath
Free list
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches
Allow one instruction to branch multiple directions
Infinite register renaming at the hardware model?
There are an infinite number of virtual registers available
Branch prediction is perfect, all conditional branches are predicted exactly
What is reducing hit time?
Cycle time at memory latency is -
the minimum time between unrelated requests to memory
Speculating on Exceptions “Prediction mechanism” is
exceptions are rare, so simply predicting no exceptions is very accurate
only write architecture state at commit point, so can throw away partially executed instructions after exception
How many main levels of cache memory?
What is the thread level parallelism -
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads
How many steps in instruction execution?
How many issue queue used in Centralized Superscalar 2 and exceptions?
What is a FL?
free leg
free list
free last
free launch
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time”-?
the time between when the user enters the command and the complete response is displayed
the time for the user to enter the command
What is the “issue” in pipelining basics?
Decode instructions, check for data hazard
Decode instructions, check for control hazard
Decode instructions, check for structural hazard
Little’s Law and a series of definitions lead to several useful equations for “Length queue”
Perfect jump prediction at The Hardware Model?
All jumps are perfectly predicted
Branch prediction is perfect
What is the term of dependability in SLOs?
Standard Level Offset
Standard Level Objectives
What is a FSB?
Finished store Buffer
Finished stack Buffer
Finished star Buffer
Finished stall Buffer
Out-of-order control complexity MIPS R10000 which is in control logic?
Data tags
Register name
Instruction cache
Data cache
Instruction count is –
What is the Instruction Level Parallelism?
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
What is the RLP?
Random Level Parallelism
Request Level Parallelism
Research Level Parallelism
In multilevel caches “Global miss rate” equals:
What does mean MSHR?
Miss Status Handling Register
Memory status handling register
mips status hardware prefetching
map status handling reload
What is the spatial locality?
