Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Integer Datapath
CLK
Free List
Address Queue
What is “VLIW”?
Very Long Instruction Word
Very Less Interpreter Word
Very Light Internal Word
Very Low Invalid Word
At VLIW by “performance and loop iteration” which time is longer?
Loop Unrolled
Software Pipelined
At VLIW by “performance and loop iteration” which time is shorter?
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Speculative operations that don’t cause exceptions
Hardware to check pointer hazards
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
What is an ALAT? :
Advanced Load Address Table
Allocated Link Address Table
Allowing List Address Table
Addition Long Accessibility Table
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Allow one instruction to branch multiple directions
What is a Compulsory?
first-reference to a block, occur even with infinite cache
cache is too small to hold all data needed by program, occur even under perfect replacement policy
misses that occur because of collisions due to less than full associativity
What is a Capacity?
Convert this number systems: DEC (9578) to HEX?
256A
43B1
7DE1
A31F
Convert this number systems: DEC (9845) to HEX?
2675
2798
2945
2811
Define a boolean algebra
process that applies binary logic to yield binary results
to determine whether an IP address exists on the local network or whether it must be routed outside the local network.
It sends out ICMP (Internet Control Message Protocol) messages to verify both the logical addresses & the Physical connection.
to determine whether an IP address exists on the global network or whether it must be routed outside the global network.
Where Virtual Machine was developed?
Lancaster University
Manchester University
MIT
Cambridge
What is the first commercial computer with virtual machine
B5000
B5550
B5500
C5000
When was the first commercial computer with virtual machine released?
1961
1962
1963
1964
Which of the following is false about VM and performance?
Better performance: we can use more memory than we have
Nothing; mapping to memory or disk is just as easy
Worse performance: reading from disk is slower than RAM
Good performance: reading from disk is slower than RAM
Which of the following is false about usability of Virtual Memory?
Not enough memory
Holes in the address space
Keeping program secure
Keeping program insecure
Define virtual address space
process refers to the logical (or virtual) view of how a process is stored in memory
used to translate the virtual addresses seen by the application into physical addresses
a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
none of the mentioned
Define a page tables
Of the following, identify the memory usually written by the manufacturer.
RAM
DRAM
SRAM
ROM
Cache Memory
Multi-processor system that computer system have are also called
parallel; systems
tightly coupled system
loosely coupled system
both a and b
Which of the following statement is false?
Combinational circuits has memory
Sequential circuits has memory
Sequential circuits is a function of time
Combinational circuits does not require feedback paths
Sequential circuits require feedback paths.
The computer architecture having stored program is _____.
Harvard
Von-Neumann
Pascal
Ada
Cobol
The key technology used in IV generation computers is _______.
MSI
SSI
LSI &VLSI
Transistors
Vacuum Tubes
The digital circuit that generates the arithmetic sum of two binary numbers of any length is ________ .
Binary-Adder
Full-Adder
Half-Adder
Adder
OR-gate
Serial to parallel data conversion is done using
Accumulator
Shift Register
Counter
CPU
Control Unit
CACHE memory is implemented using ________.
Dynamic RAM
Static RAM
EA RAM
ED RAM
EP RAM
Stack is a _________list.
FIFO
LIFO
FILO
OFLI
LFIO.
Which one of the following is a memory whose duty is to store most frequently used data?
Main memory
Cache memory
Auxiliary memory
PROM.
How many bytes equals Petabyte (PB)?
Quadrillion
Million
Trillion
Billion
1000
Examples of superscalar(static):
MIPS and ARM
Pentium 4, MIPS R12K, IBM, Power5
Itanium
TI C6x
Examples of superscalar(dynamic) :
None at the present
How many main levels of Cache Memory?
3
2
6
8
What is a “Synchronization” in OS Execution?
Execution in the OS that is neither idle nor in synchronization access
Execution in user code
Execution or waiting for synchronization variables
What is a “Kernel” in OS Execution?
Which one of the following is correct?
Sequential circuit is an interconnection of only logic gates
Sequential circuit is an interconnection of only flip flops
Combinational circuit is an interconnection of logic gates
Combinational circuit is an interconnection of flip flops
Part of a combinational circuit is a sequential circuit.
Identify the expansion for RISC.
Reduced Instruction Sign Computers
Reduced Instruction Set Computers
Reduced Instruction Set Carry
Reduced Invalid Set Computers
Reset Instruction Set Computers.
Buffering the actual target instructions allows us to perform an optimization which called:
branch folding
Branch prediction
Target instructions
Target address
Which is not the function of integrated instruction fetch unit:
Instruction memory commit
Integrated branch prediction
Instruction prefetch
Instruction memory access and buffering
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Address aliasing prediction
Dynamic branch prediction
RISC stands for
Reduced Instruction Set Computer
Recall Instruction Sell Communication
Rename Instruction Sequence Corporation
Red Instruction Small Computer
The ideal pipeline CPI is a measure of …
the maximum performance attainable by the implementation
the maximum performance attainable by the instruction
the minimum performance attainable by the implementation
the minimum performance attainable by the instruction
What is the Pipeline CPI ?
Ideal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
Ideal pipeline CPU + Data hazard stalls + Control stalls
Ideal pipeline CPU + Ideal pipeline CPI + Data hazard stalls + Control stalls
Structural stalls + Data hazard stalls + Control stalls
The simplest and most common way to increase the ILP is …?
to exploit parallelism among iterations of a loop
to exploit minimalism among iterations of a loop
to destroy iterations of a loop
to decrease the minimalism of risk
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
loop-level parallelism
exploit-level parallelism
high-level minimalism
low-level minimalism
In parallelism have three different types of dependences, tagging him:
data dependences, name dependences and control dependences
data dependences, name dependences, and surname dependences
datagram dependences ,name dependences, and animal dependences
no correct answers
What is Name dependence?
name dependence occurs when two instructions use the same register or memory location
name dependence occurs when five or more instructions use the same register or memory location
name dependence occurs when instructions use the same name
All answers is correct
When occurs an output dependence?
When i and instruction j write the same register or memory location
when i and instruction j write the same name
when i and instruction j write the same address or memory location
What is RAW (read after write)?
when j tries to read a source before i writes it, so j incorrectly gets the old value
when i tries to read a source before j writes it, so j correctly gets the old value
when j tries to write a source before i writes it
when a tries to write a source before b read it, so a incorrectly gets the old value
What is given is not a hazard?
RAR
WAR
WAW
RAW
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
loop unrolling
loop-level
loop rolling
Effect that results from instruction scheduling in large code segments is called…?
register pressure
registration
The simplest dynamic branch-prediction scheme is a
branch-prediction buffer
branch buffer
All answers correct
Branch predictors that use the behavior of other branches to make a prediction are called
correlating predictors or two-level predictors
branch table
three level loop
What is the compulsory in Three C’s model?
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
The number of accesses that miss divided by the number of accesses.
None of them
What is capacity in Three C’s model?
What is conflict in Three C’s model?
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
Which of the following belongs to Cache Optimization?
Larger block size to reduce miss rate
Bigger caches to increase miss rat
Single level caches to reduce miss penalty
Choose the strategy of Sixth Cache Optimization
Critical word first
Critical restart
Sequential inter leaving
Merging Write Buffer to Reduce Miss Penalty
Choose the Seventh Cache Optimization
Nonblocking Caches to Increase Cache Bandwidth
Trace Caches to Reduce Hit Time
Choose the Tenth Cache Optimization
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
What is the access time?
Time between when a read is requested and when the desired word arrives
The minimum time between requests to memory.
Describes the technology inside the memory chips and those innovative, internal organizations
What is the cycle time?
The maximum time between requests to memory.
What does DRAM stands for?
Dynamic Random Access memory
Dual Random Access memory
Dataram Random Access memory
What does DDR stands for?
Double data rate
Dual data rate
Double data reaction
What acts as the traffic cop controlling the flow of data and coordinating interactions among components in the system?
Microprocessor
Storage device
Chipset
Instruction register stores_____________?
Data of the current instruction
Next Instruction which is to be executed
Address of the current instruction
Instruction which is currently executed
A Set of Physical Addresses is called ________________?
Pages
Address space
Disk space
Memory space
The ______________________ operation sets to 1 the bits in one register where there are corresponding?
Selective Clear
Mask
Selective Complement
Selective Set
