Which of the following problems would NOT being identified during POST?

The correct order of the boot process is:

What's the first thing the Startup BIOS looks for on a hard drive during boot up?

POST stands for:

Which of the following is NOT a motherboard form factor:

Which statement is NOT true about CMOS chips:

How many of the following components are part of the CPU?

• ALU
• Real Time Clock
• branch predictor
• Registers
• Program Counter

Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?

Which term is commonly used to reference the process of division and
multiplication of the system clock to achieve the desired frequency?

Secondary cache, also called ______ cache, may be located either in the
CPU cartridge or on the system board near the CPU.

How many of the following items are true regarding cache?
◦ Cache uses DRAM with is faster that SRAM (found in main memory)
◦ Cache is not always found in the CPU
◦ Cache is designed as temporary storage for the CPU
◦ The size of cache is matched to be equal to the amount of main memory in
the computer

Early Pentium CPUs are said to have multi-processing capabilities because they ____________

Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.

Different speeds for computer components are achieved by using what is called ___________.

Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.

The Multiplier is the term used to describe the ________________

The front side bus connects the CPU to the ______.

A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump

A unit that controls the operations of all components in the processor and executes conditional instructions

Allows access to the hard disk drive, USB ports and other I/O devices

Allows access to the RAM and video card

A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel

An internal memory location that contrains the instruction that is to be executed.

The part of the CPU that processes arithmetic and logical instructions

An internal memory location that contains the address of the next instruction to be executed

Used as temporary storage for the CPU

The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.

With 486 and higher CPUs, the cache controller is ________.

Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.

Which of the following items relieves the CPU of processing traffic to
and from all the buses and controllers on the system board?

The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.

How many of the following buses connect to the GMCH in the
Accelerated Hub Architecture Chipset?
•PCI • System
• Memory • AGP
• ISA • VESA-Local Bus

Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.

With IDE drives, the OS executes the remainder of the format process. This is known as a _____.
Select one:

Which SCSI ID would usually be used for Hard Drives?

In a process called _____, track and sector markings are written on the hard drive at the factory.

IDE drives use a _____-pin cable.

What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?

Zone Bit Recording means ___________________

Which of the following is NOT a type of parallel port?

Parallel ports transmit data in parallel, _____ bit(s) at a time.

When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.

Which of the following is true about SCSI vs EIDE?

The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?

In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.

The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.

A null-modem cable can be used to directly connect two ____ devices.

Which statement is NOT true about CMOS chips:

The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.

How many of the following statements are true?
◦ DRAM is always faster that SRAM
◦ SRAM is lower cost that DRAM
◦ Both DRAM and SRAM are available in synchronous and asynchronous forms
◦ Both SRAM and DRAM retains values when the power is off

How many of the following statements are true?
◦ DRAM does not require refreshing to hold data
◦ SRAM allows for faster data access that DRAM
◦ SRAM costs more than DRAM per byte
◦ SRAM and DRAM memory cells are the same physical size per byte

How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors

How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors

Which BUS version is set to replace AGP?

What kind of Parity checking is being used if the following byte of data and it's parity bit are correct:
Value: 1011 0111 Parity Bit: 1

Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.

What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?

You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?

One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.

The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus.
(HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)

Which of the following is a list of expansion bus types ?

The ______ ISA bus was so named because it had only an eight-bit data path.

Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.

All data stored in _____ is lost when the power is turned off.

On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)

The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.

ECC RAM differs from parity and nonparity RAM in that it can ______.