Kapitel 4 - DRAM Organisation and Access - Vocabulary

collection

grid

to split

row

column

to feed (fed)

pin

successive

to latch

proper

to await

i.e. (that is)

simultaneously

to place

to appear

delay

storage cells

strobe

split up

particular

availability

latency

measured

row/column address decoder

memory matrix

RAS (Row Address Strobe) Signal

row/column address latch

WE (Write Enable) signal

CAS (Column Address Strobe) signal

CAS Latency (CL)

nanosecond

clock cycle