Main Memory

Background
1. A program must be loaded into memory to be executed
2. CPU have direct access only to registers and main memory
3. What does memory unit see?
  1. Stream of
    1. Address + read request
    2. Address + write request
4. Time to access
  1. Registers
    1. ~1 clock cycle
  2. Main Memory
    1. Multiple clock cycles
      1. May generate stalls
5. Cache
  1. Managed by hardware
  2. Memory between CPU and main memory
  3. Faster than main memory, slower than registers
6. Protection of memory
  1. It ensures that each program only accesses segments of main memory that are allowed to them.
Memory Protection
1. Mechanism to make sure that each process will access only the segments of memory to which they are allowed
  1. Pair of registers that define the logical address space of a process: BASE and LIMIT
2. Algorithm
  1. OBS.: loading base and limit register requires high privilege
  2. CPU checks if the memory access generated in user space is valid.
Address binding
1. Source code
  1. Define symbols
    1. Ex.: name of a variable , name of a function
  2. Accessible at compile time
2. Compiled code
  1. Bind symbols from source code to Relocatable addresses
    1. Ex.: N bytes from the beginning of this module
  2. Accessible at load time
3. Linked and loaded code
  1. Bind relocatable addresses to absolute logical (?) addresses
    1. Ex. : <base_address> + N
  2. Accessible at execution time
Address space
1. Physical
  1. Seen by the memory unit
2. Logical (virtual address)
  1. Seen by the CPU
3. Memory Management Unit
  1. Translates logical address, from CPU, to physical address for the physical memory
  2. Ex.
  3. Not all systems have MMU. Less complex systems, like embedded systems, do not have MMU.
Dynamic Loading
1. Load the routines of the program only when they are called
2. Routines on disk in relocatable load format
Linking
1. Dynamic
  1. Linking happens in execution time
    1. Stub
      1. Small piece of code used to locate the appropriate memory-resident library routine. It replaces itself with the address of the routine and executes the routine.
2. Static
  1. system libs + program code = binary program image
Partitions
1. Operating Systems maintain information about: (a) - allocated partitions and (b) - free partitions.
2. Dynamic Storage-allocation problem: satisty a request of size N from a list of free holes
  1. First-fit
    1. Allocate the first hole that is big enough
  2. Best-fit
    1. Allocate the smallest hole the is big enough
  3. Worst-fit
    1. Allocate the largest hole.
  4. The first-fit and best-fit strategies are usually better in terms of speed and storage than worst-fit
3. Fragmentation
  1. External
    1. Total memory is sufficient to satisfy a request but it is not contiguous.
  2. Internal
    1. Allocated memory is larger than what is actually used.
Paging
1. It is a technique in which the physical memory is divided into fixed-size blocks (frames) of 512 B to 2 MB and logical memory into fixed-size blocks (pages).
  1. Make it possible for the program to be loaded even if no contiguous physical memory space is available but the total space is available.
    1. Ex. A program of size N pages needs N free frames to be loaded.
2. Address Translation
  1. Page Table
    1. Translates logical addresses to physical addresses.
    2. It may is stored in main memory, but it is inefficient. It is better to be assisted by a cache (TLB).
    3. Each process will have its own page table
      1. It allows using random addresses to make it harder to find the final physical address, something good for security.
    4. Implementation
      1. Registers
        Page-table Base Register
        Points to the table
        Page-table length register
        Size of the table
      2. Cache
        Translation Look-aside buffer (TLB) or (Associative Memory)
        TLB entry
        Uniquely identify each process to provide address space protection to that process
        Greater TLBs are better because they avoid miss.
    5. Structure
      1. Strategies
        Hierarchical Paging
        The idea consists of using multiple levels of page table.
        OBS.: Caches should be used to avoid multiple main memory accesses
        Ex. 1
        Ex. 2:
        Hashed Page Table
        Inverted Page Tables
  2. Logical Address
    1. Page Number
      1. It is an index for a base physical address of each page in page table.
    2. Page Offset
      1. With the base address, it defines the physical memory
  3. Ex. 1
    1. Ex. 2
      1. Ex. 3 (with TLB)
Effective Access Time (EAT)
1. Hit Ration
  1. % of times that a page number was found in TLB.
2. ETA = <Hit Ratio> x <Mean time to access memory> + <Miss Ratio> x 2 x <Mean time to access memory>
  1. OBS.: When a miss happens, it is necessary to access the memory twice. One to get information from page table and other to read/write from the memory
Protection
1. A protection bit is associated with each frame, indicating read/write or other kind of operation is allowed. A violation results in a trap to the kernel.
2. Valid-invalid bit
  1. VALID: Indicate that the associated page is in the process' logical address space
  2. INVALID: indicate that the associated page is not in the process' logical address space
Swapping
1. It is the process to move a process/page from main memory to a secondary memory temporarily.
2. Ex. of process swapping:

Next up

Main Memory

Description

Resource summary

Media attachments

Similar

	Created by Artur Assis about 2 years ago