3885825
Description
Mind Map by cristinaaa.perez, updated more than 1 year ago
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Created by cristinaaa.perez
over 8 years ago
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Truth Table, inputs-outputs
- MINILOG
- SOP
- POS
- Simplify the equations
- Transform into a VHDL file
- Example: P <= (X and Y and Z)
- ispLEVER
- Implementate
- ActiveHDL
- Simulations and results
- Simulations and results
- ActiveHDL
- Implementate
- Example: P <= (X and Y and Z)
- Transform into a VHDL file
- Simplify the equations
- SOP
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