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13651874
The Von Neumann Architecture
Description
the vn neumann architecture
No tags specified
key stage 3
Mind Map by
Harrison Huang
, updated more than 1 year ago
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Created by
Harrison Huang
almost 7 years ago
299
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Resource summary
The Von Neumann Architecture
Programme Unit
Output
Input
(Data)Memory
Accumulator
(Data)Memory
PC
CPU
ALU
ACC
MDR
Cache
CU
MAR
Address
Data
Load address 5
Add address 6
Store in address 6
End
23
12
1
2
3
4
5
6
Fetch,decode and execute instructions
Programme Counter
Memory Address Register
Memory Data Register
Accumulation
CENTRAL PROCESSING UNIT
Control Unit
Arithmetic/Logic Unit
Memory Unit
Input device
Output device
CPU
A fan that keeps the processor cool
Memory
stores the programme
Processor
Carries out the instructions
CPU
Arithmetic/Logic unit (ALU)
PC (Programme Counter)
MDR (Memory Data Register)
Cache
Control Unit
Control Unit
Sends signals to CPU
Cache
Provides fast access to frequently load instructions and data
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