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4113154
IC Target Technology
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Mind Map by
Bill Mans
, updated more than 1 year ago
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Created by
Bill Mans
about 9 years ago
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Resource summary
IC Target Technology
FPGA
advantages
small,fast and easy to create small project,agility,reduce the cost of project design,less delay
disadvantages
very hard to study, expensive than commercial chip
cost
it depend on the project, but in China it costs only 500 yuan(70-80 euro)
software support
quartus maxplus ISE
time to market
for a small project such as student number detector about one mouth
power consumption
5V DC power can let it work(less power consumption)
adaptability
it can be used to adapt all the electric device if you want to
basic hardware format
SRAM
CPLD
advantages
good logic power, less cost in project,less developing time,less delay
disadvantages
it is not a good ideal for CPLD to create large project
cost
about 200 yuan(20-30 euro) in China
software support
quartus maxplus ISE
time to market
if the project is not too large, it takes less than one mouth to market
power consumption
less power consumption
adaptability
it can be used to adapt all the electric device if you want to
basic hardware format
and or gate
Mass gate arrays
advantage
fast, the signal chip costs less(but in the beginning costs more), it can be used for a long time
disadvantage
it requires more time to develop, more money to develop the chip,can not be progessed
cost
at the begning we should spend more money in it
software support
Synopsys, Cadence, electric
time to market
much longer than FPGA and CPLD, sometime several years
power consumption
less
adaptability
not very good, it can only be used to the fixed area
basic hardware format
die
Standard cell
advantage
we can use the disign several time without redesign them, and it make the deign more queality and effective
disadvantage
it is a brand new technology and it still have time for this technology to develop,still can not program the standard cell
cost
less than mass gate arrays
software support
electric
time to market
less than mass gate arrays
power consumption
less
adaptability
better than mass gate array but if only in design time, when it come to the chip it's adaptability is also very poor
basic hardware format
in side is logic gates, outside is standard cell(a module which can realize some function)
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