What is a Latency:
is time for a single access – Main memory latency is usually >> than processor cycle time
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
is amount of data that can be in flight at the same time (Little’s Law)
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
n loop iterations
subroutine call
vector access
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Cache HIT:
No Write Allocate, Write Allocate
Write Through, Write Back
Cache MISS:
Average Memory Access Time is equal:
Hit Time * ( Miss Rate + Miss Penalty )
Hit Time - ( Miss Rate + Miss Penalty )
Hit Time / ( Miss Rate - Miss Penalty )
Hit Time + ( Miss Rate * Miss Penalty )
The formula of “Iron Law” of Processor Performance:
time/program = instruction/program * cycles/instruction * time/cycle
time/program = instruction/program * cycles/instruction + time/cycle
time/program = instruction/program + cycles/instruction * time/cycle
Structural Hazard:
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
An instruction depends on a data value produced by an earlier instruction
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Data Hazard:
Control Hazard:
What is a Bandwidth:
a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
What is a Bandwidth-Delay Product:
What is Computer Architecture?
is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Least Recently Used (LRU):
cache state must be updated on every access
Used in highly associative caches
FIFO with exception for most recently used block(s)
Cache Hit -
Write Through – write both cache and memory, generally higher traffic but simpler to design
Write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
No Write Allocate – only write to main memory
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
If cache size is doubled, miss rate usually drops by about √2
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
None of them
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
What is the access time?
Time between when a read is requested and when the desired word arrives
The minimum time between requests to memory.
Describes the technology inside the memory chips and those innovative, internal organizations
What is the cycle time?
The maximum time between requests to memory.
What does SRAM stands for?
Static Random Access memory
System Random Access memory
Short Random Access memory
What does DRAM stands for?
Dynamic Random Access memory
Dual Random Access memory
Dataram Random Access memory
Which one is concerning to fallacy?
Predicting cache performance of one program from another
Simulating enough instructions to get accurate performance measures of the memory hierarchy
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
Over emphasizing memory bandwidth in DRAMs
Which one is NOT concerning to pitfall?
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
The time between when the user enters the command and the complete response is displayed
The time for the user to enter the command
The time from the reception of the response until the user begins to enter the next command
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
Average time per task in the queue
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Little’s Law and a series of definitions lead to several useful equations for “Time system” -
Little’s Law and a series of definitions lead to several useful equations for “Length server” -
Average number of tasks in service
Average length of queue
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
Select two-dimensional interconnection network
Mesh
Linear Array
Cross Bar
Select multi-dimensional interconnection network
Cube
Hyper Cube
