Operations performed by a processor, such as fetching an instruction, decoding the instruction, performing an arithmetic operation, and so on, are governed by:
a system clock
a system processor
a clock processor
a processor
a clock
Typically all operations performed by a processor begin with the:
pulse of the clock
pulse of the processor
it begins by itself
both of clock and processor pulse
none of the above
The time between pulses called?
clock speed
clock rate
cycle time
clock cycle
cycle rate
Typically, clock signals are generated by a ______, which generates a constant signal wave while power is applied.
quartz crystal
calcium crystal
zinc crystal
mercury crystal
radium crystal
A processor is driven by a clock with a constant frequency f or, equivalently, a constant cycle time t, where t = 1/f:
Instruction execution rate
Instruction execution cycle
Instruction execution time
Instruction execution period
None of the above
Average cycles per instruction of a program called:
CPU
Clock cycle time
CPI
Clock rate
CPE
__ is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.
A benchmark suite
A performance suite
A IDE suite
A MIPS suite
Measures such as MIPS and MFLOPS have proven adequate to evaluating the performance of processors
SPEC Benchmarks, which evaluates the performance of World Wide Web (WWW) servers:
SPECjvm98
SPECjbb2000
SPECweb99
SPECmail2001
all of the above
SPEC Benchmarks, which intended to evaluate performance of the combined hardware and software aspects of the Java Virtual Machine (JVM) client platform:
SPEC Benchmarks, which for evaluating server-side Java-based electronic commerce applications:
SPEC Benchmarks, which designed to measure a system’s performance acting as a mail server
ENIAC stands for:
Electronic Numerical Integrator and Computer
Electronic Nuclear Integrator and Computer
Encapsulation Numerical Integrator and Commerce
Encapsulation Numerical Integrator and Computer
Electronic Numerical Integer and Computer
The general structure of the IAS computer:
main memory
arithmetic and logic unit
control unit
Input/output equipment
Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit
Memory buffer register (MBR)
Memory address register (MAR)
Instruction register (IR)
Instruction buffer register (IBR)
Program counter (PC)
Specifies the address in memory of the word to be written from or read into the MBR
Contains the 8-bit opcode instruction being executed.
Employed to hold temporarily the right-hand instruction from a word in memory
Contains the address of the next instruction pair to be fetched from memory.
Transistor is a solid-state device, made from silicon
The use of the _______ defines the second generation of computers.
Vacuum tube
Transistor
Small- and medium-scale integration
Large-scale integration
Very-large-scale integration
The use of the _______ defines the first generation of computers.
The use of the ________ defines the third generation of computers.
The use of the _________ defines the fourth generation of computers.
The use of the _________ defines the fifth generation of computers.
Moore’s law: “The cost of a chip has remained virtually unchanged during this period of rapid growth in density. This means that the cost of computer logic and memory circuitry has increasing at a dramatic
Moore’s law: “Because logic and memory elements are placed closer together on more densely packed chips, the electrical path length is shortened, decreasing operating speed”
Moore’s law: “The computer becomes smaller, making it more convenient to place in a variety of environments”
Moore’s law: “There is a reduction in power and cooling requirements”
Moore’s law: “The interconnections on the integrated circuit are much more reliable than solder connections. With less circuitry on each chip, there are fewer interchip connections”
When Intel was developed its 4004, it is the first chip to contain all of the components of a CPU on a single chip, later known as Microprocessor
1973
1971
1972
1974
1970
Processor can simultaneously work on multiple instructions. How this technique called?
Branch prediction
Pipelining
Data flow analysis
Speculative execution
The processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next
The processor analyzes which instructions are dependent on each other’s results, or data, to create an optimized schedule of instructions
This enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed
The “natural” unit of organization of memory
Word
Addressable units
Unit of transfer
Sequential access
Direct access
For main memory, this is the number of bits read out of or written into memory at a time
Memory is organized into units of data, called records; access must be made in a specific linear sequence
For random-access memory, this is the time it takes to perform a read or write operation
Access time
Memory cycle time
Transfer rate
Performance
All of the above
The L2 cache is slower and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
The L2 cache is faster and typically larger than the L1 cache, and the L3 cache is slower and typically larger than the L2 cache
Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches
Bus watching with write through
Hardware transparency
Noncacheable memory
Software transparency
Each cache controller monitors the address lines to detect write operations to memory by other bus masters
Only a portion of main memory is shared by more than one processor, and this is designated as:
Larger blocks increase the number of blocks that fit into a cache; because each block fetch overwrites older cache contents, a small number of blocks results in data being overwritten shortly after they are fetched
A state in which data requested for processing by a component or application is found in the cache memory
cache hit
cache miss
cache overwrites
cache set
cache access time
The basic element of a semiconductor memory is:
memory cell
cache memory
RAM
DRAM
RAID stands for
Random Access Integral Disk
Redundant Access Integral Disk
Random Array Independent Disk
Redundant Array Independent Disk
Redundant Access Independent Disk
Data are recorded on and later retrieved from the disk via a conducting coil named the tail
