The main computer that stores the files that can be sent to computers that are networked together is...?:
Clip art
Mother board
Peripheral
File server
Addressing mode used in instruction: add r1, r2, r3 is?
Register
Indirect
Base
Immediate
In generic microprocessor instruction time is…?
Exactly same as machine cycle time
Shorter than machine cycle time
Larger than machine cycle time
Ten times machine cycle time
Hardware devices that are not part of the main computer system and are often added later to the system?
Highlight
Execute
Using a(n) _____ protocol, the sender and the receiver are synchronized by a signal called a clock
synchronous
asynchronous
analogue
block
The bandwidth of a(n) _____ signal is usually measured in bits per second.
video
digital
satellite
analog
A communications _____ is a physical path or frequency for a signal transmission.
band
channel
protocol
bridge
Which of the following terms represents the transmission capacity of a communications channel?
Indexing
Frequency
Bandwidth
Resolution
How many parts of Memory Hierarchy?
5
4
2
3
In Memory Hierarchy, at the Outboard storage which of the following are included:
Cache
Main memory
Magnetic tape
Magnetic disk
In Memory Hierarchy, at the Off-line storage which of the following are included:
In Memory Hierarchy, at the Inboard memory which of the following are included:
Optical disk
Cache Design has these properties?
Size, block size, mapping function, replacement algorithm, write policy
Size, search function, write function, read policy, vector algorithm
Size, mapping algorithm, vector function, write policy, replacement function
Size, blocking algorithm, search function, replacement vector, read policy
Three techniques are possible for I/O operations:
Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
Object-oriented I/O, Design I/O, Usable I/O
Machine I/O, Architecture I/O, Hardware I/O
Control I/O, Status I/O, Transfer I/O
How many principles has Deadlock?
6
Which of the following principles has Deadlock?
Prevention, Avoidance, Detection
Execution, Association, Starvation
Exclusion, Avoidance, Starvation
Starvation, Detection, Exclusion
Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Availability, confidentiality, data integrity, authenticity
Safety, accountability, reliability, density
Usability, integrity, confidentiality, reliability
Flexibility, availability, accountability, authenticity
The central themes of operating system design are all concerned with the management of processes and threads?
Multiprogramming, multiprocessing, distributed processing
Multitasking, multiprogramming, multithreading
Multiprocessing, uniprocessing, multitasking
Multithreading, distributed processing, uniprocessing
Can you solve the Dining Philosophers’ Problem using monitors?
yes
no
Assembly line operation is also called as?
Superscalar operation
pipelining process
Von-Neumann cycle
None of the mentioned
The CISC stands for?
Computer Instruction Set Compliment
Complete Instruction Set Compliment
Computer Indexed Set Components
Complex Instruction Set Computer
The secondary effect that results from instruction scheduling in large code segments is called ____?
Aggressive instruction
Correlating predictors
Register predictors
Register pressure
How many instructions can be implemented in MIPS?
2 clock cycles
3 clock cycles
4 clock cycles
5 clock cycles
What do you call the given statement as: “The number successful accesses to memory stated as a fraction.”
Hit rate
Miss rate
Success rate
Access rate5 clock cycles
Of the following, identify the memory usually written by the manufacturer.
RAM
DRAM
ROM
Cache memory
The Sun micro systems processors usually follow _____ architecture
CISC
ISA
ULTRA SPARC
RISC
The iconic feature of the RISC machine among the following are
Reduced number of addressing modes
Increased memory size
Having a branch delay slot
All of the above
Pipe-lining is a unique feature of _
СISC
IANA
Performance of a machine is determined by:
Instruction count, Clock cycle time, Clock cycles per instruction
Instruction count, Clock cycle time, Correlating predictors
Clock cycle time, Correlating predictors, Aggressive instruction
Clock cycle time, Clock cycles per instruction, Correlating predictors
What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
SRAM
Definition of Block:
minimum unit that is present or not present
location of block in memory
percentage of time item not found in upper level
memory closer to processor
time to access upper level
Definition of Block address:
What is the total number of writes?
196
784
512
1024
What is the total number of writes that miss in the cache?
588
25%
12,5%
What is the total number of writes that hit in the cache?
Suppose that we want to enhance the processor used for Web serving. The new processor is 10 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
≈ 1.86
≈ 1.96
≈ 1.56
1.30
Suppose that we want to enhance the processor used for Web serving. The new processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
≈ 1.25
Suppose that we want to enhance the processor used for Web serving. The new processor is 5 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 50% of the time and is waiting for I/O 50% of the time, what is the overall speedup gained by incorporating the enhancement?
≈ 1,67
Suppose that we want to enhance the processor used for Web serving. The new processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 30% of the time and is waiting for I/O 70% of the time, what is the overall speedup gained by incorporating the enhancement?
≈ 1.18
What is a RISC?
Reduced Instruction Set Computer
Rational Interruptible Security Computer
Research Interconnect Several Computer
When single-processor performance improvement has dropped?
2003
2004
2002
How much in percentage single-processor performance improvement has dropped to less than?
22
11
33
What is the RLP?
Research Level Parallelism
Random Level Parallelism
Request Level Parallelism
How many classes of computers classified?
7
Which distance of price has Clusters/warehouse-scale computers?
100 000 - 200 000 000 $
5 000 – 10 000 000 $
100 – 100 000 $
What is the PMD in computer classes?
Percentage map device
Powerful markup distance
Peak maze development
Personal mobile device
The Application of Brokerage operations how many cost of downtime per hour?
8 870 000 $
6 450 000 $
7 550 000 $
What is the Vector Architectures and Graphic Processor Units (GPUs) -
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
What is the Thread Level Parallelism -
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
What is the Request Level Parallelism:
What is the Instruction Level Parallelism:
What is the MISD one of the categories of computers?
Multiple Instructions Streams, Single Data Stream
Multiple Instruction Streams, Multiple Data Streams
Multiple Instruction Streams, Set Data Stream
How many elements in Trends of Technology?
How many elements of the Instruction Set Architecture (ISA):
What is a ARF:
Architectural Register File
Architecture Relocation File
Architecture Reload File
Architectural Read File
What is a ROB?
Reorder Buffer
Read Only Buffer
Reload Buffer
Recall Buffer
What is a FSB?
Finished Store Buffer
Finished Stack Buffer
Finished Stall Buffer
Finished Star Buffer
What is a PRF?
Physical Register File
Pending Register File
Pipeline Register File
Pure Register File
What is a SB?
Scoreboard
Scorebased
Scaleboard
Scalebit
How many stages used in Superscalar (Pipeline)?
What is about Superscalar means “F-D-X-M-W”?
Fetch, Decode, Execute, Memory, Writeback
Fetch, Decode, Instruct, Map, Write
Fetch, Decode, Excite, Memory, Write
Fetch, Decode, Except, Map, Writeback
Speculating on Exceptions “Prediction mechanism” is -
Exceptions are rare, so simply predicting no exceptions is very accurate
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
Only write architectural state at commit point, so can throw away partially executed instructions after exception
none
Speculating on Exceptions “Check prediction mechanism” is -
The way in which an object is accessed by a subject
Speculating on Exceptions “Recovery mechanism” is -
An entity capable of accessing objects
What is a RT?
Rename Table
Recall Table
Relocate Table
Remove Table
What is a FL?
Free List
Free Last
Free Leg
Free Launch
What is an IQ?
Issue Queue
Internal Queue
Interrupt Queue
Instruction Queue
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Width and Lifetime
Width and Height
Time and Cycle
Length and Addition
Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Register name
Instruction cache
Data tags
Data cache
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