CSA IITU Part 1 (235)

Question

130. How many bytes equals Petabyte (PB)?

Answer 1

· Quadrillion

Answer 2

· Million

Answer 3

· Trillion

Answer 4

· Billion

Answer 5

· Main memory

Answer 6

· Auxiliary memory

Answer 7

· Binary Adder

Answer 8

· Full Adder

Answer 9

· Half Adder

Answer 10

· OR gate

Answer 11

· LSI & VLSI

Answer 12

· Transistors

Answer 13

· Vacuum Tubes

Answer 14

· Harvard

Answer 15

· Von Neumann

Answer 16

· Dynamic RAM

Answer 17

· Static RAM

Answer 18

· Don’t care

Answer 19

· cache is too small to hold all data needed by program, occur even under perfect replacement policy

Answer 20

· first-reference to a block, occur even with infinite cache

Answer 21

· misses that occur because of collisions due to less than full associativity

Answer 22

· first-reference to a block, occur even with infinite cache

Answer 23

· cache is too small to hold all data needed by program, occur even under perfect replacement policy

Answer 24

· misses that occur because of collisions due to less than full associativity

Answer 25

Multiple Instruction Streams, Multiple Data Streams

Answer 26

Multiple Instructions Streams, Single Data Stream

Answer 27

Multiple Instruction Streams, Set Data Stream

Answer 28

Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution

Answer 29

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 30

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 31

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 32

Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads

Answer 33

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 34

Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads

Answer 35

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 36

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 37

Exploits data-level parallelism at modest levels with computer help using ideas like pipelining and at medium levels using ideas like speculative execution

Answer 38

Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Answer 39

Exploits parallelism among largely decoupled tasks specified by the programmer or operating system

Answer 40

8.870.000$

Answer 41

7.550.000$

Answer 42

6.450.000$

Answer 43

Percentage map device

Answer 44

Personal mobile device

Answer 45

Peak maze development

Answer 46

Powerful markup distance

Answer 47

100 – 100.000$

Answer 48

100.000 – 200.000.000$

Answer 49

5.000 – 10.000.000$

Answer 50

Request Level Parallelism

Answer 51

Research Level Parallelism

Answer 52

Random Level Parallelism

Answer 53

Rational Interruptible Security Computer

Answer 54

Research Interconnect Several Computer

Answer 55

Reduced Instruction Set Computer

Answer 56

Average Memory Access time = Hit Time + Miss Rate * Miss penalty

Answer 57

Average Memory Access time = Hit Rate + Miss Rate * Miss penalty

Answer 58

Average Memory Access time = Hit Time + Miss time * Miss penalty

Answer 59

Average Memory Access time = Hit Rate + Miss time * Miss penalty

Answer 60

minimum unit that is presented or not present

Answer 61

location of block in memory

Answer 62

percentage of item not found in upper level

Answer 63

time to access upper level

Answer 64

memory closer to processor

Answer 65

minimum unit that is presented or not present

Answer 66

location of block in memory

Answer 67

percentage of item not found in upper level

Answer 68

memory closer to processor

Answer 69

time to access upper level

Answer 70

Instruction count, Clock cycle time, Correlating predictors

Answer 71

Instruction count, Clock cycle time, Clock cycle per instruction

Answer 72

Clock cycle time, Correlating predictors, Aggressive instruction

Answer 73

Clock cycle time, Clock cycles per instruction, Correlating Predictors

Answer 74

Increased memory size

Answer 75

Reduced number of addressing modes

Answer 76

Having a branch delay slot

Answer 77

All of the above

Answer 78

ULTRA SPARC

Answer 79

Cache Memory

Answer 80

Access rate

Answer 81

Success rate

Answer 82

2 clock cycles

Answer 83

3 clock cycles

Answer 84

4 clock cycles

Answer 85

5 clock cycles

Answer 86

Aggressive instruction

Answer 87

Correlating predictors

Answer 88

Register predictors

Answer 89

Register pressure

Answer 90

Computer Instruction Set Compliment

Answer 91

Complete Instruction Set Compliment

Answer 92

Computer Indexed Set Components

Answer 93

Complex Instruction Set Computer

Answer 94

Pipelining process

Answer 95

Superscalar operation

Answer 96

None of the mentioned

Answer 97

Von Neumann cycle

Answer 98

Yes, but only if there are less than five philosophers

Answer 99

No, unless there are more than five philosophers

Answer 100

Multiprogramming, multiprocessing, distributed processing

Answer 101

Multitasking, multiprogramming, multithreading

Answer 102

Multiprocessing, uniprocessing, multitasking

Answer 103

Multithreading, distributed processing, uniprocessing

Answer 104

Availability, confidentiality, data integrity, authenticity

Answer 105

Safety, accountability, reliability, density

Answer 106

Usability, integrity, confidentiality, reliability

Answer 107

Flexibility, availability, accountability, authenticity

Answer 108

Execution, Association, Starvation

Answer 109

Prevention, Avoidance, Detection

Answer 110

Starvation, Detection, Exclusion

Answer 111

Exclusion, Avoidance, Starvation

Answer 112

Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)

Answer 113

Machine I/O, Architecture I/O, Hardware I/O

Answer 114

Object-oriented I/O, Design I/O, Usable I/O

Answer 115

Control I/O, Status I/O, Transfer I/O

Answer 116

Size, search function, write function, read policy, vector algorithm

Answer 117

Size, mapping algorithm, vector function, write policy, replacement function

Answer 118

Size, blocking algorithm, search function, replacement vector, read policy

Answer 119

Size, block size, mapping function, replacement algorithm, write policy

Answer 120

Magnetic disk

Answer 121

Magnetic tape

Answer 122

Optical disk

Answer 123

Main memory

Answer 124

• Magnetic disk

Answer 125

• Magnetic tape

Answer 126

• Main memory

Answer 127

• Main memory

Answer 128

• Magnetic tape

Answer 129

• Magnetic disk

Answer 130

o Predicting cache performance of one program from another

Answer 131

o Simulating enough instructions to get accurate performance measures of the memory hierarchy

Answer 132

o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

Answer 133

o Over emphasizing memory bandwidth in DRAMs

Answer 134

o Simulating enough instructions to get accurate performance measures of the memory hierarchy

Answer 135

o Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable

Answer 136

o Over emphasizing memory bandwidth in DRAMs

Answer 137

o Predicting cache performance of one program from another

Answer 138

o Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate

Answer 139

o Merging Write Buffer to Reduce Miss Penalty

Answer 140

o Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate

Answer 141

o None of them

Answer 142

o Merging Write Buffer to Reduce Miss Penalty

Answer 143

o Critical word ﬁrst

Answer 144

o Nonblocking Caches to Increase Cache Bandwidth

Answer 145

o Trace Caches to Reduce Hit Time

Answer 146

o Critical restart

Answer 147

o Critical word ﬁrst

Answer 148

o Sequential inter leaving

Answer 149

o Merging Write Buffer to Reduce Miss Penalty

Answer 150

o Larger block size to reduce miss rate

Answer 151

o Bigger caches to increase miss rat

Answer 152

o Single level caches to reduce miss penalty

Answer 153

o None of them

Answer 154

o If the block placement strategy is not fully associative, conﬂict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conﬂicting blocks map to its set

Answer 155

o The very ﬁrst access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an inﬁnite cache.

Answer 156

o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 157

o None of them

Answer 158

o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 159

o The very ﬁrst access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an inﬁnite cache.

Answer 160

o The number of accesses that miss divided by the number of accesses.

Answer 161

o None of them

Answer 162

o The very ﬁrst access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an inﬁnite cache.

Answer 163

o The number of accesses that miss divided by the number of accesses.

Answer 164

o None of them

Answer 165

o If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved

Answer 166

o the number of prediction entries selected by the branch = 1K.

Answer 167

o the number of prediction entries selected by the branch = 2K.

Answer 168

o the number of prediction entries selected by the branch = 8K.

Answer 169

o the number of prediction entries selected by the branch = 4K.

Answer 170

o correlating predictors or two-level predictors

Answer 171

o branch-prediction buffer

Answer 172

o branch table

Answer 173

o three level loop

Answer 174

o branch-prediction buffer

Answer 175

o branch buffer

Answer 176

o All answers correct

Answer 177

o registrationo registration

Answer 178

o register pressure

Answer 179

o loop unrolling

Answer 180

o loop-level

Answer 181

o registration

Answer 182

o loop unrolling

Answer 183

o loop-level

Answer 184

o loop rolling

Answer 185

o when j tries to read a source before i writes it, so j incorrectly gets the old value

Answer 186

o when j tries to write a source before i writes it

Answer 187

o when i tries to read a source before j writes it, so j correctly gets the old value

Answer 188

o when a tries to write a source before b read it, so a incorrectly gets the old value

Answer 189

o When i and instruction j write the same register or memory location

Answer 190

o when i and instruction j write the same adress or memory location

Answer 191

o when i and instruction j write the same name

Answer 192

o All answers is correct

Answer 193

o name dependence occurs when two instructions use the same register or memory location

Answer 194

o name dependence occurs when five or more instructions use the same register or memory location

Answer 195

o name dependence occurs when instructions use the same name

Answer 196

o All answers is correct

Answer 197

o data dependences , name dependences , and surname dependences

Answer 198

o datagram dependences , name dependences , and animal dependences

Answer 199

o no correct answers

Answer 200

o data dependences , name dependences , and control dependences

Answer 201

o loop-level parallelism

Answer 202

o exploit-level parallelism

Answer 203

o high-level minimalism

Answer 204

o low-level minimalism

Answer 205

o to exploit parallelism among iterations of a loop

Answer 206

o to exploit minimalism among iterations of a loop

Answer 207

o to destroy iterations of a loop

Answer 208

o to decrease the minimalism of risk

Answer 209

o deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls

Answer 210

o deal pipeline CPU + Data hazard stalls + Control stalls

Answer 211

o deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls

Answer 212

o Structural stalls + Data hazard stalls + Control stalls

Answer 213

o the maximum performance attainable by the implementation

Answer 214

o the maximum performance attainable by the instruction

Answer 215

o the minimum performance attainable by the implementation

Answer 216

o the minimum performance attainable by the instruction

Answer 217

o Reduced Instruction Set Computer

Answer 218

o Recall Instruction Sell Communication

Answer 219

o Rename Instruction Sequence Corporation

Answer 220

o Red Instruction Small Computer

Answer 221

o Address aliasing prediction

Answer 222

o Branch prediction

Answer 223

o Integrated branch prediction

Answer 224

o Dynamic branch prediction

Answer 225

o Instruction memory commit

Answer 226

o Integrated branch prediction

Answer 227

o Instruction memory access and buffering

Answer 228

o Instruction prefetch

Answer 229

o branch folding

Answer 230

o Branch prediction

Answer 231

o Target instructions

Answer 232

o Target address

Answer 233

o branch-target buffer

Answer 234

o data buffer

Answer 235

o frame buffer

Answer 236

o optical buffer

Answer 237

o MIPS and ARM

Answer 238

o Pentium 4, MIPS R12K, IBM, Power5

Answer 239

o None at the present

Answer 240

o Pentium 4, MIPS R12K, IBM, Power5

Answer 241

o MIPS and ARM

Answer 242

• MIPS and ARM

Answer 243

o Pentium 4, MIPS R12K, IBM, Power5

Answer 244

o MIPS and ARM

Answer 245

o Pentium 4, MIPS R12K, IBM, Power5

Answer 246

o Superscalar(dynamic)

Answer 247

o Superscalar(static)

Answer 248

o Superscalar(speculative)

Answer 249

o statistically superscalar processors

Answer 250

o dynamically scheduled superscalar processors

Answer 251

o statically scheduled superscalar processors

Answer 252

o VLIW (very long instruction word) processors

Answer 253

o issue, execute, write result, commit

Answer 254

o execution, commit, rollback

Answer 255

o issue, execute, override, exit

Answer 256

o begin, write, interrupt, commit

Answer 257

o the instruction type, the destination field, the value field, and the ready field

Answer 258

o the source type, the destination field, the value field, and the ready field

Answer 259

o the program type, the ready field, the parameter field, the destination field

Answer 260

o the instruction type, the destination field, and the ready field

Answer 261

o To pass parameters through instructions that may be speculated

Answer 262

o To pass results among instructions that may be speculated.

Answer 263

o To get additional registers in the same way as the reservation stations

Answer 264

o To control registers

Answer 265

o data flow execution

Answer 266

o data control execution

Answer 267

o instruction execution

Answer 268

o instruction field execution

Answer 269

o Functional unit capability

Answer 270

o Clock rate

Answer 271

o Popular data structure for organizing a large collection of data items so that one can quickly answer questions

Answer 272

o Popular tables for organizing a large collection of data structure

Answer 273

o Popular data structure for updating large collections, so that one can hardly answer questions

Answer 274

o Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Answer 275

o Achievable ILP with software resource constraints

Answer 276

o Limited ILP due to software dependences

Answer 277

o Achievable ILP with hardware resource constraints

Answer 278

o Variability of ILP due to software and hardware interaction

Answer 279

o Dynamic power

Answer 280

o Processing rate

Answer 281

o Static power

Answer 282

o Processor state

Answer 283

o Static power

Answer 284

o Dynamic power

Answer 285

o Processing rate

Answer 286

o Processor state

Answer 287

o We must fetch more, issue more, and initiate execution on more than four instructions

Answer 288

o We must fetch less, issue more, and initiate execution on more than two instructions

Answer 289

o We must fetch more, issue more, and initiate execution on less than five instructions

Answer 290

o We must fetch more, issue less, and initiate execution on more than three instructions

Answer 291

o The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate

Answer 292

o The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate

Answer 293

o The number of transistors switching will be proportional to the sustained rate

Answer 294

o The performance is proportional to the peak issue rate

Answer 295

o Increasing multithreading

Answer 296

o Increasing performance

Answer 297

o Increasing multiple cores

Answer 298

o Increasing multithreading(повторяется хз что тут )

Answer 299

o Proportional to the product of the number of switching transistors and the switching rate

Answer 300

o Grows proportionally to the transistor count (whether or not the transistors are switching)

Answer 301

o Certainly a design concern

Answer 302

o None of the above

Answer 303

o Grows proportionally to the transistor count (whether or not the transistors are switching)

Answer 304

o Proportional to the product of the number of switching transistors and the switching rate Probability

Answer 305

o Proportional to the product of the number of switching transistors and the switching rate

Answer 306

o All of the above

Answer 307

o Efficiency

Answer 308

o Probability

Answer 309

• 90% 10%

Answer 310

o mean time to failure

Answer 311

o mean time to feauture

Answer 312

o mean this to failure

Answer 313

o my transfers to failure

Answer 314

o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA

Answer 315

o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA

Answer 316

o 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Answer 317

o 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Answer 318

o 30% to 48%

Answer 319

o 4% to 12%

Answer 320

o 15% to 30%

Answer 321

o 1% to 17%

Answer 322

o the learning curve

Answer 323

o the cycled line

Answer 324

o the regular option

Answer 325

o the final loop

Answer 326

o dynamic power

Answer 327

o physical energy

Answer 328

o constant supply

Answer 329

o simple battery

Answer 330

o feature size

Answer 331

o permanent size n

Answer 332

o compex size

Answer 333

o fixed size

Answer 334

o commodities

Answer 335

o bandwidth

Answer 336

o throughput

Answer 337

o performance

Answer 338

o bandwidth

Answer 339

o throughput

Answer 340

o performance

Answer 341

o performance of swithes and transmission system

Answer 342

o performance of switches

Answer 343

o has no dependensies

Answer 344

o performance of transmission system

Answer 345

o Execution in the OS that is neither idle nor in synchronization access

Answer 346

o Execution or waiting for synchronization variables

Answer 347

o Execution in user code

Answer 348

o Execution in user code

Answer 349

o Execution in the OS that is neither idle nor in synchronization access

Answer 350

o Execution or waiting for synchronization variables

Answer 351

o Execution or waiting for synchronization variables

Answer 352

o Execution in the OS that is neither idle nor in synchronization access

Answer 353

o Execution in user code

Answer 354

o Execution in the OS that is neither idle nor in synchronization access

Answer 355

o Execution in user code

Answer 356

o Execution or waiting for synchronization variables

	Criado por Hello World quase 7 anos atrás

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CSA IITU Part 1 (235)

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