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PC_architecture_Final_Preparation

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PC Arc Quiz sobre PC_architecture_Final_Preparation, criado por Alisher Kassymov em 22-05-2018.
Alisher Kassymov
Quiz por Alisher Kassymov , atualizado more than 1 year ago
Alisher Kassymov
Criado por Alisher Kassymov mais de 6 anos atrás
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18
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Resumo de Recurso

Questão 1

Questão
What is a Latency:
Responda
  • is amount of data that can be in flight at the same time (Little’s Law)
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is time for a single access – Main memory latency is usually >> than processor cycle time

Questão 2

Questão
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • n loop iterations
  • subroutine call
  • vector access

Questão 3

Questão
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • n loop iterations
  • subroutine call
  • vector access

Questão 4

Questão
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Responda
  • subroutine call
  • n loop iterations
  • vector access

Questão 5

Questão
Cache HIT:
Responda
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Questão 6

Questão
Cache MISS:
Responda
  • No Write Allocate, Write Allocate
  • Write Through, Write Back

Questão 7

Questão
Average Memory Access Time is equal:
Responda
  • Hit Time * ( Miss Rate + Miss Penalty )
  • Hit Time - ( Miss Rate + Miss Penalty )
  • Hit Time / ( Miss Rate - Miss Penalty )
  • Hit Time + ( Miss Rate * Miss Penalty )

Questão 8

Questão
Compulsory -
Responda
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Questão 9

Questão
Capacity -
Responda
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • first-reference to a block, occur even with infinite cache

Questão 10

Questão
Conflict -
Responda
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Questão 11

Questão
Algorithm for Cache HIT:
Responda
  • Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache
  • Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
  • Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return copy of data from cache

Questão 12

Questão
Algorithm for Cache MISS:
Responda
  • Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
  • Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
  • Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from cache

Questão 13

Questão
The formula of “Iron Law” of Processor Performance:
Responda
  • time/program = instruction/program * cycles/instruction * time/cycle
  • time/program = instruction/program * cycles/instruction + time/cycle
  • time/program = instruction/program + cycles/instruction * time/cycle

Questão 14

Questão
Structural Hazard:
Responda
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Questão 15

Questão
Data Hazard:
Responda
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • An instruction depends on a data value produced by an earlier instruction

Questão 16

Questão
Control Hazard:
Responda
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline

Questão 17

Questão
What is a Bandwidth:
Responda
  • a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is amount of data that can be in flight at the same time (Little’s Law)

Questão 18

Questão
What is a Bandwidth-Delay Product:
Responda
  • is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
  • is time for a single access – Main memory latency is usually >> than processor cycle time
  • is amount of data that can be in flight at the same time (Little’s Law)

Questão 19

Questão
What is Computer Architecture?
Responda
  • the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
  • is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
  • is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users

Questão 20

Questão
Least Recently Used (LRU):
Responda
  • FIFO with exception for most recently used block(s)
  • Used in highly associative caches
  • cache state must be updated on every access

Questão 21

Questão
Cache Hit -
Responda
  • Write Through – write both cache and memory, generally higher traffic but simpler to design
  • write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
  • No Write Allocate – only write to main memory

Questão 22

Questão
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Responda
  • None of them
  • If cache size is doubled, miss rate usually drops by about √2
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2

Questão 23

Questão
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Responda
  • Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
  • None of them
  • If cache size is doubled, miss rate usually drops by about √2

Questão 24

Questão
Exploit temporal locality:
Responda
  • by remembering the contents of recently accessed locations
  • by fetching blocks of data around recently accessed locations
  • None of them

Questão 25

Questão
Exploit spatial locality:
Responda
  • None of them
  • by remembering the contents of recently accessed locations
  • by fetching blocks of data around recently accessed locations

Questão 26

Questão
Structural Hazard:
Responda
  • An instruction depends on a data value produced by an earlier instruction
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction

Questão 27

Questão
Data Hazard:
Responda
  • An instruction in the pipeline needs a resource being used by another instruction in the pipeline
  • Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
  • An instruction depends on a data value produced by an earlier instruction

Questão 28

Questão
What is the access time?
Responda
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • None of them

Questão 29

Questão
What is the cycle time?
Responda
  • The minimum time between requests to memory
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of them

Questão 30

Questão
What does SRAM stands for?
Responda
  • System Random Access memory
  • Static Random Access memory
  • Short Random Accessmemory
  • None of them

Questão 31

Questão
What does DRAM stands for?
Responda
  • Dataram Random Access memory
  • Dual Random Access memory
  • Dynamic Random Access memory

Questão 32

Questão
What does DDR stands for?
Responda
  • None of them
  • Double data reaction
  • Dual data rate
  • Double data rate

Questão 33

Questão
What is kernel process?
Responda
  • Provide at least two modes, indicating whether the running process is a user process or an operating system process
  • Provide a portion of the processor state that a user process can use but not write
  • Provide at least five modes, indicating whether the running process is a user process or an operating system process
  • None of them

Questão 34

Questão
Which one is NOT concerning to pitfall?
Responda
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Predicting cache performance of one program from another
  • Over emphasizing memory bandwidth in DRAMs

Questão 35

Questão
Which one is concerning to fallacy?
Responda
  • Over emphasizing memory bandwidth in DRAMs
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy

Questão 36

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Responda
  • The time from the reception of the response until the user begins to enter the next command
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command

Questão 37

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Responda
  • The time from the reception of the response until the user begins to enter the next command
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command

Questão 38

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Responda
  • Average time per task in the queue
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts

Questão 39

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Responda
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
  • Average time per task in the queue
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Questão 40

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Responda
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
  • Average time per task in the queue

Questão 41

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Responda
  • Average length of queue
  • Average number of tasks in service

Questão 42

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
Responda
  • Average length of queue
  • Average number of tasks in service

Questão 43

Questão
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Responda
  • 4
  • 3
  • 2
  • 1

Questão 44

Questão
How many issue queue used in Distributed Superscalar 2 and Exceptions:
Responda
  • 4
  • 3
  • 1
  • 2

Questão 45

Questão
How many instructions used in Distributed Superscalar 2 and Exceptions?
Responda
  • 4
  • 3
  • 2
  • 1

Questão 46

Questão
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Responda
  • 1
  • 2
  • 3
  • 4

Questão 47

Questão
Which of the following formula is true about Issue Queue for “Instruction Ready”:
Responda
  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
  • Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
  • Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
  • Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards

Questão 48

Questão
What is a ARF:
Responda
  • Architectural Register File
  • Architecture Relocation File
  • Architecture Reload File
  • Architectural Read File

Questão 49

Questão
What is a ROB?
Responda
  • Read Only Buffer
  • Reorder Buffer
  • Reload Buffer
  • Recall Buffer

Questão 50

Questão
What is a FSB?
Responda
  • Finished Star Buffer
  • Finished Stall Buffer
  • Finished Store Buffer
  • Finished Stack Buffer

Questão 51

Questão
What is a PRF?
Responda
  • Pure Register File
  • Physical Register File
  • Pending Register File
  • Pipeline Register File

Questão 52

Questão
What is a SB?
Responda
  • Scalebit
  • Scaleboard
  • Scorebased
  • Scoreboard

Questão 53

Questão
How many stages used in Superscalar (Pipeline)?
Responda
  • 5
  • 4
  • 6
  • 7

Questão 54

Questão
What is about Superscalar means “F-D-X-M-W”?
Responda
  • Fetch, Decode, Instruct, Map, Write
  • Fetch, Decode, Execute, Memory, Writeback
  • Fetch, Decode, Excite, Memory, Write
  • Fetch, Decode, Except, Map, Writeback

Questão 55

Questão
Speculating on Exceptions “Prediction mechanism” is -
Responda
  • None of them
  • Only write architectural state at commit point, so can throw away partially executed instructions after exception
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types

Questão 56

Questão
Speculating on Exceptions “Check prediction mechanism” is -
Responda
  • The way in which an object is accessed by a subject
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • None of them

Questão 57

Questão
Speculating on Exceptions “Recovery mechanism” is
Responda
  • None of them
  • An entity capable of accessing objects
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • Only write architectural state at commit point, so can throw away partially executed instructions after exception

Questão 58

Questão
What is a RT?
Responda
  • Rename Table
  • Recall Table
  • Relocate Table
  • Remove Table

Questão 59

Questão
What is a FL?
Responda
  • Free Launch
  • Free List
  • Free Leg
  • Free Last

Questão 60

Questão
What is an IQ?
Responda
  • Internal Queue
  • Instruction Queue
  • Issue Queue
  • Interrupt Queue

Questão 61

Questão
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Responda
  • Width and Height
  • Width and Lifetime
  • Time and Cycle
  • Length and Addition

Questão 62

Questão
Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Responda
  • Register name
  • Instruction cache
  • Data tags
  • Data cache

Questão 63

Questão
Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Responda
  • Integer Datapath
  • CLK
  • Address Queue
  • Free List

Questão 64

Questão
What is “VLIW”?
Responda
  • Very Less Interpreter Word
  • Very Long Instruction Word
  • Very Light Internal Word
  • Very Low Invalid Word

Questão 65

Questão
At VLIW by “performance and loop iteration” which time is longer?
Responda
  • Loop Unrolled
  • Software Pipelined

Questão 66

Questão
At VLIW by “performance and loop iteration” which time is shorter?
Responda
  • Loop Unrolled
  • Software Pipelined

Questão 67

Questão
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Responda
  • Hardware to check pointer hazards
  • Speculative operations that don’t cause exceptions

Questão 68

Questão
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Responda
  • Hardware to check pointer hazards
  • Speculative operations that don’t cause exceptions

Questão 69

Questão
What is an ALAT? :
Responda
  • Advanced Load Address Table
  • Allocated Link Address Table
  • Allowing List Address Table
  • Addition Long Accessibility Table

Questão 70

Questão
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Responda
  • Allow one instruction to branch multiple directions
  • Speculative operations that don’t cause exceptions

Questão 71

Questão
What is a Compulsory?
Responda
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • misses that occur because of collisions due to less than full associativity

Questão 72

Questão
What is a Capacity?
Responda
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • misses that occur because of collisions due to less than full associativity
  • first-reference to a block, occur even with infinite cache

Questão 73

Questão
What is a Conflict?
Responda
  • misses that occur because of collisions due to less than full associativity
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy

Questão 74

Questão
In Multilevel Caches “Local miss rate” equals =
Responda
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses
  • misses in cache / number of instructions

Questão 75

Questão
In Multilevel Caches “Global miss rate” equals =
Responda
  • misses in cache / CPU memory accesses
  • misses in cache / accesses to cache
  • misses in cache / number of instructions

Questão 76

Questão
In Multilevel Caches “Misses per instruction” equals =
Responda
  • misses in cache / number of instructions
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses

Questão 77

Questão
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
Responda
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Questão 78

Questão
Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Responda
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time

Questão 79

Questão
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
Responda
  • CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
  • CPU time-Cache Miss-Miss Penalty-CPU time
  • CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time

Questão 80

Questão
What does mean MSHR?
Responda
  • Miss Status Handling Register
  • Map Status Handling Reload
  • Mips Status Hardware Register
  • Memory Status Handling Register

Questão 81

Questão
What does MAF?
Responda
  • Miss Address File
  • Map Address File
  • Memory Address File

Questão 82

Questão
At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking Cache “Order of fill”:
Responda
  • 0,1,2,3,4,5,6,7
  • 3,4,5,6,7,0,1,2

Questão 83

Questão
At Critical Word First for Miss Penalty chose correct sequence of Blocking Cache with Critical Word first “Order of fill”:
Responda
  • 3,4,5,6,7,0,1,2
  • 0,1,2,3,4,5,6,7

Questão 84

Questão
Storage Systems, “Larger block size to reduce miss rate”
Responda
  • The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses

Questão 85

Questão
Storage Systems, “Bigger caches to reduce miss rate” -
Responda
  • The obvious way to reduce capacity misses is to increase cache capacity
  • Obviously, increasing associativity reduces conflict misses
  • The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size

Questão 86

Questão
Storage Systems, “Higher associativity to reduce miss rate” -
Responda
  • Obviously, increasing associativity reduces conflict misses
  • The obvious way to reduce capacity misses is to increase cache capacity
  • The simplest way to reduce the miss rate is to take advantage of spatial locality and increase the block size

Questão 87

Questão
In Non-Blocking Caches what does mean “Critical Word First”?
Responda
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution

Questão 88

Questão
In Non-Blocking Caches what does mean “Early restart”?
Responda
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Questão 89

Questão
A virus classification by target includes the following categories, What is a File infector?
Responda
  • A typical approach is as follows
  • Infects files that the operating system or shell consider to be executable
  • The key is stored with the virus
  • Far more sophisticated techniques are possible

Questão 90

Questão
What is a RAID 0?
Responda
  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
  • Also called mirroring or shadowing, there are two copies of every piece of data
  • This organization was inspired by applying memory-style error correcting codes to disks

Questão 91

Questão
What is a RAID 1?
Responda
  • Also called mirroring or shadowing, there are two copies of every piece of data
  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
  • This organization was inspired by applying memory-style error correcting codes to disks

Questão 92

Questão
What is a RAID 2?
Responda
  • This organization was inspired by applying memory-style error correcting codes to disks
  • It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although the data may be striped across the disks in the array
  • Also called mirroring or shadowing, there are two copies of every piece of data

Questão 93

Questão
What is a RAID 3?
Responda
  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
  • Many applications are dominated by small accesses
  • Also called mirroring or shadowing, there are two copies of every piece of data

Questão 94

Questão
What is a RAID 4?
Responda
  • Many applications are dominated by small accesses
  • Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
  • Also called mirroring or shadowing, there are two copies of every piece of data

Questão 95

Questão
At storage systems Gray and Siewiorek classify faults what does mean “Hardware faults”? :
Responda
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Faults in software (usually) and hardware design (occasionally)
  • Mistakes by operations and maintenance personnel

Questão 96

Questão
At storage systems Gray and Siewiorek classify faults what does mean “Design faults”? :
Responda
  • Faults in software (usually) and hardware design (occasionally)
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Mistakes by operations and maintenance personnel

Questão 97

Questão
At storage systems Gray and Siewiorek classify faults what does mean “Operation faults”? :
Responda
  • Mistakes by operations and maintenance personnel
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
  • Faults in software (usually) and hardware design (occasionally)

Questão 98

Questão
At storage systems Gray and Siewiorek classify faults what does mean “Environmental faults”? :
Responda
  • Fire, flood, earthquake, power failure, and sabotage
  • Faults in software (usually) and hardware design (occasionally)
  • Devices that fail, such as perhaps due to an alpha particle hitting a memory cell

Questão 99

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Entry time” - ? :
Responda
  • The time for the user to enter the command
  • The time between when the user enters the command and the complete response is displayed
  • The time from the reception of the response until the user begins to enter the next command

Questão 100

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?:
Responda
  • The time between when the user enters the command and the complete response is displayed
  • The time for the user to enter the command
  • The time from the reception of the response until the user begins to enter the next command

Questão 101

Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?:
Responda
  • The time from the reception of the response until the user begins to enter the next command
  • The time for the user to enter the command
  • The time between when the user enters the command and the complete response is displayed

Questão 102

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time server” - :
Responda
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time per task in the queue

Questão 103

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time queue” - :
Responda
  • Average time per task in the queue
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server

Questão 104

Questão
Little’s Law and a series of definitions lead to several useful equations for “Time system” - :
Responda
  • Average time/task in the system, or the response time, which is the sum of Time queue and Time server
  • Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol μ in many queuing texts
  • Average time per task in the queue

Questão 105

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length server” - :
Responda
  • Average number of tasks in service
  • Average length of queue

Questão 106

Questão
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -:
Responda
  • Average length of queue
  • Average number of tasks in service

Questão 107

Questão
How many size of Cache L1 is true approximately? :
Responda
  • 8 KB
  • 256 KB
  • 2 MB

Questão 108

Questão
How many size of Cache L2 is true approximately?
Responda
  • 256 KB
  • 4 KB
  • 32 MB

Questão 109

Questão
How many size of Cache L3 is true approximately?
Responda
  • 3 MB
  • 256 MB
  • 256 KB

Questão 110

Questão
How many main levels of Cache Memory?
Responda
  • 3
  • 2
  • 6
  • 8

Questão 111

Questão
What is a “Synchronization” in Cache Memory?
Responda
  • Execution or waiting for synchronization variables
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code

Questão 112

Questão
What is a “Kernel” in Cache Memory?
Responda
  • Execution or waiting for synchronization variables
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code

Questão 113

Questão
What is a “Synchronization” in Cache Memory?
Responda
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code
  • Execution or waiting for synchronization variables

Questão 114

Questão
Network performance depends of what?
Responda
  • performance of swithes and transmission system
  • performance of switches
  • performance of transmission system
  • has no dependensies

Questão 115

Questão
The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Responda
  • latency
  • bandwidth
  • throughput
  • performance

Questão 116

Questão
Total amount of work done in a given time ,such as megabytes per second for disk transfer...
Responda
  • bandwidth
  • latency
  • throughput
  • performance

Questão 117

Questão
Learning curve itself is best measured by change in...
Responda
  • yeld
  • bytes
  • bits
  • seconds

Questão 118

Questão
Products that are sold by multiple vendors in large volumes and are essentialy identical
Responda
  • commodities
  • boxes
  • folders
  • files

Questão 119

Questão
Integrated circuit processes are charecterized by the
Responda
  • feature size
  • permanent size n
  • compex size
  • fixed size

Questão 120

Questão
For CMOS chips, the traditional dominant energy consumption has been in switching transistors, called ____
Responda
  • dynamic power
  • physical energy
  • constant supply
  • simple battery

Questão 121

Questão
Manufacturing costs that decrease over time are ____
Responda
  • the learning curve
  • the cycled line
  • the regular option
  • the final loop

Questão 122

Questão
Volume is a ________ key factor in determining cost
Responda
  • second
  • first
  • fifth
  • third

Questão 123

Questão
The most companies spend only ____________ of their income on R&D, which includes all engineering.
Responda
  • 4% to 12%
  • 15% to 30%
  • 1% to 17%
  • 30% to 48%

Questão 124

Questão
Systems alternate between two states of service with respect to an SLA:
Responda
  • 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is different from the SLA
  • 1. Service accomplishment, where the service is not delivered as specified 2. Service interruption, where the delivered service is not different from the SLA
  • 1. Service accomplishment, where the service is delivered as specified 2. Service interruption, where the delivered service is not different from the SLA

Questão 125

Questão
Desktop benchmarks divide into __ broad classes:
Responda
  • two
  • three
  • four
  • five

Questão 126

Questão
What MTTF means:
Responda
  • mean time to failure
  • mean time to feauture
  • mean this to failure
  • my transfers to failure

Questão 127

Questão
A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Responda
  • 90% 10%
  • 50% 50%
  • 70% 30%
  • 89% 11%

Questão 128

Questão
(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Responda
  • Speedup
  • Efficiency
  • Probability
  • Ration

Questão 129

Questão
Which of the following descriptions corresponds to static power?
Responda
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Proportional to the product of the number of switching transistors and the switching rate Probability
  • Proportional to the product of the number of switching transistors and the switching rate
  • All of the above

Questão 130

Questão
Which of the following descriptions corresponds to dynamic power?
Responda
  • Proportional to the product of the number of switching transistors and the switching rate
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Certainly a design concern
  • None of the above

Questão 131

Questão
Which of the written below is NOT increase power consumption?
Responda
  • Increasing multithreading
  • Increasing performance
  • Increasing multiple cores
  • Increasing multithreading (V baze tak napisano)

Questão 132

Questão
Growing performance gap between peak and sustained performance translates to increasing energy per unit of performance, when:
Responda
  • The number of transistors switching will be proportional to the peak issue rate, and the performance is proportional to the sustained rate
  • The number of transistors switching will be proportionalto the sustained rate, and the performance is proportionalto the peak issue rate
  • The number of transistors switching will be proportional to the sustained rate
  • The performance is proportional to the peak issue rate

Questão 133

Questão
If we want to sustain four instructions per clock
Responda
  • We must fetch more, issue more, and initiate execution on more than four instructions
  • We must fetch less, issue more, and initiate execution on more than two instructions
  • We must fetch more, issue less, and initiate execution on more than three instructions
  • We must fetch more, issue more, and initiate execution on less than five instructions

Questão 134

Questão
If speculation were perfect, it could save power, since it would reduce the execution time and save _____________, while adding some additional overhead to implement
Responda
  • Static power
  • Dynamic power
  • Processing rate
  • Processor state

Questão 135

Questão
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires additional ___________ both for the incorrect speculation and for the resetting of the processor state
Responda
  • Dynamic power
  • Static power
  • Processing rate
  • Processor state

Questão 136

Questão
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W. Sias
Responda
  • Achievable ILP with software resource constraints
  • Limited ILP due to software dependences
  • Achievable ILP with hardware resource constraints
  • Variability of ILP due to software and hardware interaction

Questão 137

Questão
What is a hash table?
Responda
  • Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • Popular data structure for updating large collections, so that one can hardly answer questions
  • Popular tables for organizing a large collection of data structure
  • Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Questão 138

Questão
Which of these is NOT characteristics of recent highperformance microprocessors?
Responda
  • Color
  • Power
  • Functional unit capability
  • Clock rate

Questão 139

Questão
How this process called: “Operations execute as soon as their operands are available”
Responda
  • data flow execution
  • instruction execution
  • data control execution
  • instruction field execution

Questão 140

Questão
For what the reorder buffer is used :
Responda
  • To pass results among instructions that may be speculated
  • To pass parameters through instructions that may be speculated
  • To get additional registers in the same way as the reservation stations
  • To control registers

Questão 141

Questão
How many fields contains the entry in the ROB:
Responda
  • 4
  • 5
  • 6
  • 3

Questão 142

Questão
Choose correct fields of entry in the ROB:
Responda
  • the instruction type, the destination field, the value field, and the ready field
  • the source type, the destination field, the value field, and the ready field
  • the program type, the ready field, the parameter field, the destination field
  • the instruction type, the destination field, and the ready field

Questão 143

Questão
Choose the steps of instruction execution:
Responda
  • issue, execute, write result, commit
  • execution, commit, rollback
  • issue, execute, override, exit
  • begin, write, interrupt, commit

Questão 144

Questão
Which one is not the major flavor of Multiple-issue processors
Responda
  • statistically superscalar processors
  • dynamically scheduled superscalar processors
  • statically scheduled superscalar processors
  • VLIW (very long instruction word) processors

Questão 145

Questão
Which Multiple-issue processors has not the hardware hazard detection
Responda
  • EPIC
  • Superscalar(dynamic)
  • Superscalar(static)
  • Superscalar(speculative)

Questão 146

Questão
Examples of EPIC:
Responda
  • Itanium
  • Pentium 4, MIPS R12K, IBM, Power5
  • MIPS and ARM
  • TI C6x

Questão 147

Questão
Examples of superscalar(static):
Responda
  • MIPS and ARM
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • TI C6x

Questão 148

Questão
Examples of superscalar(dynamic) :
Responda
  • None at the present
  • Pentium 4, MIPS R12K, IBM, Power5
  • MIPS and ARM
  • TI C6x

Questão 149

Questão
Examples of VLIW/LIW:
Responda
  • TI C6x
  • MIPS and ARM
  • Itanium
  • Pentium 4, MIPS R12K, IBM, Power5

Questão 150

Questão
A branch-prediction cache that stores the predicted address for the next instruction after a branch
Responda
  • branch-target buffer
  • data buffer
  • frame buffer
  • optical buffer

Questão 151

Questão
Buffering the actual target instructions allows us to perform an optimization which called:
Responda
  • branch folding
  • Branch prediction
  • Target instructions
  • Target address

Questão 152

Questão
Which is not the function of integrated instruction fetch unit:
Responda
  • Instruction memory commit
  • Integrated branch prediction
  • Instruction prefetch
  • Instruction memory access and buffering

Questão 153

Questão
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Responda
  • Address aliasing prediction
  • Branch prediction
  • Integrated branch prediction
  • Dynamic branch prediction

Questão 154

Questão
How to decrypt RISC?
Responda
  • Reduced Instruction Set Computer
  • Recall Instruction Sell Communication
  • Rename Instruction Sequence Corporation
  • Red Instruction Small Computer

Questão 155

Questão
The ideal pipeline CPI is a measure of …
Responda
  • the maximum performance attainable by the implementation
  • the maximum performance attainable by the instruction
  • the minimum performance attainable by the implementation
  • the minimum performance attainable by the instruction

Questão 156

Questão
What is the Pipeline CP = ?
Responda
  • deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • deal pipeline CPU + Data hazard stalls + Control stalls
  • deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
  • Structural stalls + Data hazard stalls + Control stalls

Questão 157

Questão
The simplest and most common way to increase the ILP is …?
Responda
  • to exploit parallelism among iterations of a loop
  • to exploit minimalism among iterations of a loop
  • to destroy iterations of a loop
  • to decrease the minimalism of risk

Questão 158

Questão
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Responda
  • loop-level parallelism
  • exploit-level parallelism
  • high-level minimalism
  • low-level minimalism

Questão 159

Questão
In parallelism have three different types of dependences, tagging him:
Responda
  • data dependences , name dependences , and control dependences
  • data dependences , name dependences , and surname dependences
  • datagram dependences , name dependences , and animal dependences
  • no correct answers

Questão 160

Questão
What is Name dependence?
Responda
  • name dependence occurs when two instructions use the same register or memory location
  • name dependence occurs when five or more instructions use the same register or memory location
  • name dependence occurs when instructions use the same name
  • All answers is correct

Questão 161

Questão
When occurs an output dependence?
Responda
  • When i and instruction j write the same register or memory location
  • when i and instruction j write the same name
  • when i and instruction j write the same adress or memory location
  • All answers is correct

Questão 162

Questão
What is RAW (read after write)?
Responda
  • when j tries to read a source before i writes it, so j incorrectly gets the old value
  • when i tries to read a source before j writes it, so j correctly gets the old value
  • when j tries to write a source before i writes it
  • when a tries to write a source before b read it, so a incorrectly gets the old value

Questão 163

Questão
What is given is not a hazard?
Responda
  • RAR
  • WAR
  • WAW
  • LOL

Questão 164

Questão
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Responda
  • loop unrolling
  • RAR
  • loop-level
  • loop rolling

Questão 165

Questão
Effect that results from instruction scheduling in large code segments is called…?
Responda
  • register pressure
  • loop unrolling
  • loop-level
  • registration

Questão 166

Questão
The simplest dynamic branch-prediction scheme is a
Responda
  • branch-prediction buffer
  • branch buffer
  • All answers correct
  • registration

Questão 167

Questão
Branch predictors that use the behavior of other branches to make a prediction are called
Responda
  • correlating predictors or two-level predictors
  • branch-prediction buffer
  • branch table
  • three level loop

Questão 168

Questão
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Responda
  • the number of prediction entries selected by the branch = 1K.
  • the number of prediction entries selected by the branch = 2K.
  • the number of prediction entries selected by the branch = 8K.
  • the number of prediction entries selected by the branch = 4K.

Questão 169

Questão
What is the compulsory in Cs model?
Responda
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The number of accesses that miss divided by the number of accesses.
  • None of them

Questão 170

Questão
What is capacityin Cs model?
Responda
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • The number of accesses that miss divided by the number of accesses.
  • None of them

Questão 171

Questão
What is conflict in Cs model?
Responda
  • If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • None of them

Questão 172

Questão
Choose the benefit of Cache Optimization.
Responda
  • Larger block size to reduce miss rate
  • Bigger caches to increase miss rat
  • Single level caches to reduce miss penalty
  • None of them

Questão 173

Questão
Choose the strategy of Seventh Optimization.
Responda
  • Critical word first
  • Critical restart
  • Sequential inter leaving
  • Merging Write Buffer to Reduce Miss Penalty

Questão 174

Questão
Choose the Eight Optimization
Responda
  • Merging Write Buffer to Reduce Miss Penalty
  • Critical word first
  • Nonblocking Caches to Increase Cache Bandwidth
  • Trace Caches to Reduce Hit Time

Questão 175

Questão
Choose the Eleventh Optimization
Responda
  • Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • Merging Write Buffer to Reduce Miss Penalty
  • Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • None of them

Questão 176

Questão
What is the access time?
Responda
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • None of them

Questão 177

Questão
What is the cycle time?
Responda
  • The minimum time between requests to memory
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of them

Questão 178

Questão
How much in percentage single-processor performance improvement has dropped to less than?
Responda
  • 11%
  • 22%
  • 33%

Questão 179

Questão
How many elements of the Instruction Set Architecture (ISA):
Responda
  • 6
  • 7
  • 8

Questão 180

Questão
What is the Thread Level Parallelism –
Responda
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Questão 181

Questão
What is the PMD in computer classes?
Responda
  • Personal mobile device
  • Powerful markup distance
  • Percentage map device

Questão 182

Questão
What is the Instruction Level Parallelism:
Responda
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel

Questão 183

Questão
How many elements in Trends of Technology?
Responda
  • 5
  • 6
  • 4

Questão 184

Questão
What is the Vector Architecture and Graphic Processor Units (GPUs) –
Responda
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a medium levels using ideas like speculative execution
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Questão 185

Questão
How many Optimizations’ in Cache memory Performance?
Responda
  • 8
  • 6
  • 10

Questão 186

Questão
What is the Reducing the Miss Rate?
Responda
  • Time Optimization
  • Compiler Optimization
  • Performance Optimization

Questão 187

Questão
What is the Spatial Locality?
Responda
  • Exploit by fetching blocks of data around recently accessed locations
  • Exploit by remembering the contents of recently accessed locations

Questão 188

Questão
What is the Temporal Locality?
Responda
  • Exploit by fetching blocks of data around recently accessed locations
  • Exploit by remembering the contents of recently accessed locations

Questão 189

Questão
True formula of Module availability (MTTF – mean time to failure, MTTR – mean time to repair)?
Responda
  • MTTF / (MTTF + MTTR)
  • MTTF * (MTTF + MTTR)
  • MTTF * (MTTF - MTTR)

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