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CSA Last p2

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Quiz sobre CSA Last p2, criado por Last Quickly em 30-03-2019.
Last Quickly
Quiz por Last Quickly, atualizado more than 1 year ago
Last Quickly
Criado por Last Quickly mais de 5 anos atrás
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Resumo de Recurso

Questão 1

Questão
Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Responda
  • Integer Datapath
  • CLK
  • Free List
  • Address Queue

Questão 2

Questão
What is “VLIW”?
Responda
  • Very Long Instruction Word
  • Very Less Interpreter Word
  • Very Light Internal Word
  • Very Low Invalid Word

Questão 3

Questão
At VLIW by “performance and loop iteration” which time is longer?
Responda
  • Loop Unrolled
  • Software Pipelined

Questão 4

Questão
At VLIW by “performance and loop iteration” which time is shorter?
Responda
  • Software Pipelined
  • Loop Unrolled

Questão 5

Questão
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Responda
  • Speculative operations that don’t cause exceptions
  • Hardware to check pointer hazards

Questão 6

Questão
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Responda
  • Hardware to check pointer hazards
  • Speculative operations that don’t cause exceptions

Questão 7

Questão
What is an ALAT? :
Responda
  • Advanced Load Address Table
  • Allocated Link Address Table
  • Allowing List Address Table
  • Addition Long Accessibility Table

Questão 8

Questão
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Responda
  • Allow one instruction to branch multiple directions
  • Speculative operations that don’t cause exceptions

Questão 9

Questão
What is a Compulsory?
Responda
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • misses that occur because of collisions due to less than full associativity

Questão 10

Questão
What is a Capacity?
Responda
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity

Questão 11

Questão
Convert this number systems: DEC (9578) to HEX?
Responda
  • 256A
  • 43B1
  • 7DE1
  • A31F

Questão 12

Questão
Convert this number systems: DEC (9845) to HEX?
Responda
  • 2675
  • 2798
  • 2945
  • 2811

Questão 13

Questão
Define a boolean algebra
Responda
  • process that applies binary logic to yield binary results
  • to determine whether an IP address exists on the local network or whether it must be routed outside the local network.
  • It sends out ICMP (Internet Control Message Protocol) messages to verify both the logical addresses & the Physical connection.
  • to determine whether an IP address exists on the global network or whether it must be routed outside the global network.

Questão 14

Questão
Where Virtual Machine was developed?
Responda
  • Lancaster University
  • Manchester University
  • MIT
  • Cambridge

Questão 15

Questão
What is the first commercial computer with virtual machine
Responda
  • B5000
  • B5550
  • B5500
  • C5000

Questão 16

Questão
When was the first commercial computer with virtual machine released?
Responda
  • 1961
  • 1962
  • 1963
  • 1964

Questão 17

Questão
Which of the following is false about VM and performance?
Responda
  • Better performance: we can use more memory than we have
  • Nothing; mapping to memory or disk is just as easy
  • Worse performance: reading from disk is slower than RAM
  • Good performance: reading from disk is slower than RAM

Questão 18

Questão
Which of the following is false about usability of Virtual Memory?
Responda
  • Not enough memory
  • Holes in the address space
  • Keeping program secure
  • Keeping program insecure

Questão 19

Questão
Define virtual address space
Responda
  • process refers to the logical (or virtual) view of how a process is stored in memory
  • used to translate the virtual addresses seen by the application into physical addresses
  • a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
  • none of the mentioned

Questão 20

Questão
Define a page tables
Responda
  • process refers to the logical (or virtual) view of how a process is stored in memory
  • used to translate the virtual addresses seen by the application into physical addresses
  • a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
  • none of the mentioned

Questão 21

Questão
Of the following, identify the memory usually written by the manufacturer.
Responda
  • RAM
  • DRAM
  • SRAM
  • ROM
  • Cache Memory

Questão 22

Questão
Multi-processor system that computer system have are also called
Responda
  • parallel; systems
  • tightly coupled system
  • loosely coupled system
  • both a and b

Questão 23

Questão
Which of the following statement is false?
Responda
  • Combinational circuits has memory
  • Sequential circuits has memory
  • Sequential circuits is a function of time
  • Combinational circuits does not require feedback paths
  • Sequential circuits require feedback paths.

Questão 24

Questão
The computer architecture having stored program is _____.
Responda
  • Harvard
  • Von-Neumann
  • Pascal
  • Ada
  • Cobol

Questão 25

Questão
The key technology used in IV generation computers is _______.
Responda
  • MSI
  • SSI
  • LSI &VLSI
  • Transistors
  • Vacuum Tubes

Questão 26

Questão
The digital circuit that generates the arithmetic sum of two binary numbers of any length is ________ .
Responda
  • Binary-Adder
  • Full-Adder
  • Half-Adder
  • Adder
  • OR-gate

Questão 27

Questão
Serial to parallel data conversion is done using
Responda
  • Accumulator
  • Shift Register
  • Counter
  • CPU
  • Control Unit

Questão 28

Questão
CACHE memory is implemented using ________.
Responda
  • Dynamic RAM
  • Static RAM
  • EA RAM
  • ED RAM
  • EP RAM

Questão 29

Questão
Stack is a _________list.
Responda
  • FIFO
  • LIFO
  • FILO
  • OFLI
  • LFIO.

Questão 30

Questão
Which one of the following is a memory whose duty is to store most frequently used data?
Responda
  • Main memory
  • Cache memory
  • ROM
  • Auxiliary memory
  • PROM.

Questão 31

Questão
How many bytes equals Petabyte (PB)?
Responda
  • Quadrillion
  • Million
  • Trillion
  • Billion
  • 1000

Questão 32

Questão
Examples of superscalar(static):
Responda
  • MIPS and ARM
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • TI C6x

Questão 33

Questão
Examples of superscalar(dynamic) :
Responda
  • None at the present
  • Pentium 4, MIPS R12K, IBM, Power5
  • MIPS and ARM
  • TI C6x

Questão 34

Questão
How many main levels of Cache Memory?
Responda
  • 3
  • 2
  • 6
  • 8

Questão 35

Questão
What is a “Synchronization” in OS Execution?
Responda
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code
  • Execution or waiting for synchronization variables

Questão 36

Questão
What is a “Kernel” in OS Execution?
Responda
  • Execution or waiting for synchronization variables
  • Execution in the OS that is neither idle nor in synchronization access
  • Execution in user code

Questão 37

Questão
Which one of the following is correct?
Responda
  • Sequential circuit is an interconnection of only logic gates
  • Sequential circuit is an interconnection of only flip flops
  • Combinational circuit is an interconnection of logic gates
  • Combinational circuit is an interconnection of flip flops
  • Part of a combinational circuit is a sequential circuit.

Questão 38

Questão
Identify the expansion for RISC.
Responda
  • Reduced Instruction Sign Computers
  • Reduced Instruction Set Computers
  • Reduced Instruction Set Carry
  • Reduced Invalid Set Computers
  • Reset Instruction Set Computers.

Questão 39

Questão
Buffering the actual target instructions allows us to perform an optimization which called:
Responda
  • branch folding
  • Branch prediction
  • Target instructions
  • Target address

Questão 40

Questão
Which is not the function of integrated instruction fetch unit:
Responda
  • Instruction memory commit
  • Integrated branch prediction
  • Instruction prefetch
  • Instruction memory access and buffering

Questão 41

Questão
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Responda
  • Address aliasing prediction
  • Branch prediction
  • Integrated branch prediction
  • Dynamic branch prediction

Questão 42

Questão
RISC stands for
Responda
  • Reduced Instruction Set Computer
  • Recall Instruction Sell Communication
  • Rename Instruction Sequence Corporation
  • Red Instruction Small Computer

Questão 43

Questão
The ideal pipeline CPI is a measure of …
Responda
  • the maximum performance attainable by the implementation
  • the maximum performance attainable by the instruction
  • the minimum performance attainable by the implementation
  • the minimum performance attainable by the instruction

Questão 44

Questão
What is the Pipeline CPI ?
Responda
  • Ideal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
  • Ideal pipeline CPU + Data hazard stalls + Control stalls
  • Ideal pipeline CPU + Ideal pipeline CPI + Data hazard stalls + Control stalls
  • Structural stalls + Data hazard stalls + Control stalls

Questão 45

Questão
The simplest and most common way to increase the ILP is …?
Responda
  • to exploit parallelism among iterations of a loop
  • to exploit minimalism among iterations of a loop
  • to destroy iterations of a loop
  • to decrease the minimalism of risk

Questão 46

Questão
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Responda
  • loop-level parallelism
  • exploit-level parallelism
  • high-level minimalism
  • low-level minimalism

Questão 47

Questão
In parallelism have three different types of dependences, tagging him:
Responda
  • data dependences, name dependences and control dependences
  • data dependences, name dependences, and surname dependences
  • datagram dependences ,name dependences, and animal dependences
  • no correct answers

Questão 48

Questão
What is Name dependence?
Responda
  • name dependence occurs when two instructions use the same register or memory location
  • name dependence occurs when five or more instructions use the same register or memory location
  • name dependence occurs when instructions use the same name
  • All answers is correct

Questão 49

Questão
When occurs an output dependence?
Responda
  • When i and instruction j write the same register or memory location
  • when i and instruction j write the same name
  • when i and instruction j write the same address or memory location
  • All answers is correct

Questão 50

Questão
What is RAW (read after write)?
Responda
  • when j tries to read a source before i writes it, so j incorrectly gets the old value
  • when i tries to read a source before j writes it, so j correctly gets the old value
  • when j tries to write a source before i writes it
  • when a tries to write a source before b read it, so a incorrectly gets the old value

Questão 51

Questão
What is given is not a hazard?
Responda
  • RAR
  • WAR
  • WAW
  • RAW

Questão 52

Questão
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Responda
  • loop unrolling
  • RAR
  • loop-level
  • loop rolling

Questão 53

Questão
Effect that results from instruction scheduling in large code segments is called…?
Responda
  • register pressure
  • loop unrolling
  • loop-level
  • registration

Questão 54

Questão
The simplest dynamic branch-prediction scheme is a
Responda
  • branch-prediction buffer
  • branch buffer
  • All answers correct
  • registration

Questão 55

Questão
Branch predictors that use the behavior of other branches to make a prediction are called
Responda
  • correlating predictors or two-level predictors
  • branch-prediction buffer
  • branch table
  • three level loop

Questão 56

Questão
What is the compulsory in Three C’s model?
Responda
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The number of accesses that miss divided by the number of accesses.
  • None of them

Questão 57

Questão
What is capacity in Three C’s model?
Responda
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • The number of accesses that miss divided by the number of accesses.
  • None of them

Questão 58

Questão
What is conflict in Three C’s model?
Responda
  • If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
  • If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
  • None of them

Questão 59

Questão
Which of the following belongs to Cache Optimization?
Responda
  • Larger block size to reduce miss rate
  • Bigger caches to increase miss rat
  • Single level caches to reduce miss penalty
  • None of them

Questão 60

Questão
Choose the strategy of Sixth Cache Optimization
Responda
  • Critical word first
  • Critical restart
  • Sequential inter leaving
  • Merging Write Buffer to Reduce Miss Penalty

Questão 61

Questão
Choose the Seventh Cache Optimization
Responda
  • Merging Write Buffer to Reduce Miss Penalty
  • Critical word first
  • Nonblocking Caches to Increase Cache Bandwidth
  • Trace Caches to Reduce Hit Time

Questão 62

Questão
Choose the Tenth Cache Optimization
Responda
  • Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
  • Merging Write Buffer to Reduce Miss Penalty
  • Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
  • None of them

Questão 63

Questão
What is the access time?
Responda
  • Time between when a read is requested and when the desired word arrives
  • The minimum time between requests to memory.
  • Describes the technology inside the memory chips and those innovative, internal organizations
  • None of them

Questão 64

Questão
What is the cycle time?
Responda
  • The minimum time between requests to memory.
  • Time between when a read is requested and when the desired word arrives
  • The maximum time between requests to memory.
  • None of them

Questão 65

Questão
What does DRAM stands for?
Responda
  • Dynamic Random Access memory
  • Dual Random Access memory
  • Dataram Random Access memory

Questão 66

Questão
What does DDR stands for?
Responda
  • Double data rate
  • Dual data rate
  • Double data reaction
  • None of them

Questão 67

Questão
What acts as the traffic cop controlling the flow of data and coordinating interactions among components in the system?
Responda
  • Microprocessor
  • Main memory
  • Storage device
  • Chipset

Questão 68

Questão
Instruction register stores_____________?
Responda
  • Data of the current instruction
  • Next Instruction which is to be executed
  • Address of the current instruction
  • Instruction which is currently executed

Questão 69

Questão
A Set of Physical Addresses is called ________________?
Responda
  • Pages
  • Address space
  • Disk space
  • Memory space

Questão 70

Questão
The ______________________ operation sets to 1 the bits in one register where there are corresponding?
Responda
  • Selective Clear
  • Mask
  • Selective Complement
  • Selective Set

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