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CSA Last p1

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God Philosophy Quiz sobre CSA Last p1, criado por хомяк убийца em 30-03-2019.
хомяк убийца
Quiz por хомяк убийца, atualizado more than 1 year ago
хомяк убийца
Criado por хомяк убийца mais de 5 anos atrás
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Resumo de Recurso

Questão 1

Questão
The main computer that stores the files that can be sent to computers that are networked together is...?:
Responda
  • Clip art
  • Mother board
  • Peripheral
  • File server

Questão 2

Questão
Addressing mode used in instruction: add r1, r2, r3 is?
Responda
  • Register
  • Indirect
  • Base
  • Immediate

Questão 3

Questão
In generic microprocessor instruction time is…?
Responda
  • Exactly same as machine cycle time
  • Shorter than machine cycle time
  • Larger than machine cycle time
  • Ten times machine cycle time

Questão 4

Questão
Hardware devices that are not part of the main computer system and are often added later to the system?
Responda
  • Peripheral
  • Clip art
  • Highlight
  • Execute

Questão 5

Questão
Using a(n) _____ protocol, the sender and the receiver are synchronized by a signal called a clock
Responda
  • synchronous
  • asynchronous
  • analogue
  • block

Questão 6

Questão
The bandwidth of a(n) _____ signal is usually measured in bits per second.
Responda
  • video
  • digital
  • satellite
  • analog

Questão 7

Questão
A communications _____ is a physical path or frequency for a signal transmission.
Responda
  • band
  • channel
  • protocol
  • bridge

Questão 8

Questão
Which of the following terms represents the transmission capacity of a communications channel?
Responda
  • Indexing
  • Frequency
  • Bandwidth
  • Resolution

Questão 9

Questão
How many parts of Memory Hierarchy?
Responda
  • 5
  • 4
  • 2
  • 3

Questão 10

Questão
In Memory Hierarchy, at the Outboard storage which of the following are included:
Responda
  • Cache
  • Main memory
  • Magnetic tape
  • Magnetic disk

Questão 11

Questão
In Memory Hierarchy, at the Off-line storage which of the following are included:
Responda
  • Cache
  • Magnetic disk
  • Magnetic tape
  • Main memory

Questão 12

Questão
In Memory Hierarchy, at the Inboard memory which of the following are included:
Responda
  • Main memory
  • Magnetic disk
  • Magnetic tape
  • Optical disk

Questão 13

Questão
Cache Design has these properties?
Responda
  • Size, block size, mapping function, replacement algorithm, write policy
  • Size, search function, write function, read policy, vector algorithm
  • Size, mapping algorithm, vector function, write policy, replacement function
  • Size, blocking algorithm, search function, replacement vector, read policy

Questão 14

Questão
Three techniques are possible for I/O operations:
Responda
  • Programmed I/O, Interrupt-driven I/O, Direct memory access(DMA)
  • Object-oriented I/O, Design I/O, Usable I/O
  • Machine I/O, Architecture I/O, Hardware I/O
  • Control I/O, Status I/O, Transfer I/O

Questão 15

Questão
How many principles has Deadlock?
Responda
  • 3
  • 5
  • 2
  • 6

Questão 16

Questão
Which of the following principles has Deadlock?
Responda
  • Prevention, Avoidance, Detection
  • Execution, Association, Starvation
  • Exclusion, Avoidance, Starvation
  • Starvation, Detection, Exclusion

Questão 17

Questão
Much of the work in security and protection as it relates to operating systems can be roughly grouped into four categories?
Responda
  • Availability, confidentiality, data integrity, authenticity
  • Safety, accountability, reliability, density
  • Usability, integrity, confidentiality, reliability
  • Flexibility, availability, accountability, authenticity

Questão 18

Questão
The central themes of operating system design are all concerned with the management of processes and threads?
Responda
  • Multiprogramming, multiprocessing, distributed processing
  • Multitasking, multiprogramming, multithreading
  • Multiprocessing, uniprocessing, multitasking
  • Multithreading, distributed processing, uniprocessing

Questão 19

Questão
Can you solve the Dining Philosophers’ Problem using monitors?
Responda
  • yes
  • no

Questão 20

Questão
Assembly line operation is also called as?
Responda
  • Superscalar operation
  • pipelining process
  • Von-Neumann cycle
  • None of the mentioned

Questão 21

Questão
The CISC stands for?
Responda
  • Computer Instruction Set Compliment
  • Complete Instruction Set Compliment
  • Computer Indexed Set Components
  • Complex Instruction Set Computer

Questão 22

Questão
The secondary effect that results from instruction scheduling in large code segments is called ____?
Responda
  • Aggressive instruction
  • Correlating predictors
  • Register predictors
  • Register pressure

Questão 23

Questão
How many instructions can be implemented in MIPS?
Responda
  • 2 clock cycles
  • 3 clock cycles
  • 4 clock cycles
  • 5 clock cycles

Questão 24

Questão
What do you call the given statement as: “The number successful accesses to memory stated as a fraction.”
Responda
  • Hit rate
  • Miss rate
  • Success rate
  • Access rate5 clock cycles

Questão 25

Questão
Of the following, identify the memory usually written by the manufacturer.
Responda
  • RAM
  • DRAM
  • ROM
  • Cache memory

Questão 26

Questão
The Sun micro systems processors usually follow _____ architecture
Responda
  • CISC
  • ISA
  • ULTRA SPARC
  • RISC

Questão 27

Questão
The iconic feature of the RISC machine among the following are
Responda
  • Reduced number of addressing modes
  • Increased memory size
  • Having a branch delay slot
  • All of the above

Questão 28

Questão
Pipe-lining is a unique feature of _
Responda
  • RISC
  • СISC
  • IANA
  • ISA

Questão 29

Questão
Performance of a machine is determined by:
Responda
  • Instruction count, Clock cycle time, Clock cycles per instruction
  • Instruction count, Clock cycle time, Correlating predictors
  • Clock cycle time, Correlating predictors, Aggressive instruction
  • Clock cycle time, Clock cycles per instruction, Correlating predictors

Questão 30

Questão
What do you call the given statement as for type of memory?: “High density, low power, cheap, slow, need to be “refreshed” regularly”
Responda
  • DRAM
  • SRAM
  • CISC
  • RAM
  • ROM

Questão 31

Questão
Definition of Block:
Responda
  • minimum unit that is present or not present
  • location of block in memory
  • percentage of time item not found in upper level
  • memory closer to processor
  • time to access upper level

Questão 32

Questão
Definition of Block address:
Responda
  • minimum unit that is present or not present
  • location of block in memory
  • percentage of time item not found in upper level
  • memory closer to processor
  • time to access upper level

Questão 33

Questão
What is the total number of writes?
Image:
Набросок (1) (binary/octet-stream)
Responda
  • 196
  • 784
  • 512
  • 1024

Questão 34

Questão
What is the total number of writes that miss in the cache?
Image:
Набросок (1) (binary/octet-stream)
Responda
  • 588
  • 196
  • 25%
  • 12,5%

Questão 35

Questão
What is the total number of writes that hit in the cache?
Image:
Набросок (1) (binary/octet-stream)
Responda
  • 588
  • 784
  • 12,5%

Questão 36

Questão
Suppose that we want to enhance the processor used for Web serving. The new processor is 10 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Responda
  • ≈ 1.86
  • ≈ 1.96
  • ≈ 1.56
  • 1.30

Questão 37

Questão
Suppose that we want to enhance the processor used for Web serving. The new processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 40% of the time and is waiting for I/O 60% of the time, what is the overall speedup gained by incorporating the enhancement?
Responda
  • ≈ 1.25
  • ≈ 1.96
  • ≈ 1.56
  • 1.30

Questão 38

Questão
Suppose that we want to enhance the processor used for Web serving. The new processor is 5 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 50% of the time and is waiting for I/O 50% of the time, what is the overall speedup gained by incorporating the enhancement?
Responda
  • ≈ 1.86
  • ≈ 1.96
  • ≈ 1,67
  • 1.30

Questão 39

Questão
Suppose that we want to enhance the processor used for Web serving. The new processor is 2 times faster on computation in the Web serving application than the original processor. Assuming that the original processor is busy with computation 30% of the time and is waiting for I/O 70% of the time, what is the overall speedup gained by incorporating the enhancement?
Responda
  • ≈ 1.86
  • ≈ 1.18
  • ≈ 1.56

Questão 40

Questão
What is a RISC?
Responda
  • Reduced Instruction Set Computer
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer

Questão 41

Questão
When single-processor performance improvement has dropped?
Responda
  • 2003
  • 2004
  • 2002

Questão 42

Questão
How much in percentage single-processor performance improvement has dropped to less than?
Responda
  • 22
  • 11
  • 33

Questão 43

Questão
What is the RLP?
Responda
  • Research Level Parallelism
  • Random Level Parallelism
  • Request Level Parallelism

Questão 44

Questão
How many classes of computers classified?
Responda
  • 7
  • 3
  • 5

Questão 45

Questão
Which distance of price has Clusters/warehouse-scale computers?
Responda
  • 100 000 - 200 000 000 $
  • 5 000 – 10 000 000 $
  • 100 – 100 000 $

Questão 46

Questão
What is the PMD in computer classes?
Responda
  • Percentage map device
  • Powerful markup distance
  • Peak maze development
  • Personal mobile device

Questão 47

Questão
The Application of Brokerage operations how many cost of downtime per hour?
Responda
  • 8 870 000 $
  • 6 450 000 $
  • 7 550 000 $

Questão 48

Questão
What is the Vector Architectures and Graphic Processor Units (GPUs) -
Responda
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Questão 49

Questão
What is the Thread Level Parallelism -
Responda
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Questão 50

Questão
What is the Request Level Parallelism:
Responda
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Questão 51

Questão
What is the Instruction Level Parallelism:
Responda
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Questão 52

Questão
What is the MISD one of the categories of computers?
Responda
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instruction Streams, Set Data Stream

Questão 53

Questão
How many elements in Trends of Technology?
Responda
  • 3
  • 4
  • 5

Questão 54

Questão
How many elements of the Instruction Set Architecture (ISA):
Responda
  • 5
  • 6
  • 7

Questão 55

Questão
What is a ARF:
Responda
  • Architectural Register File
  • Architecture Relocation File
  • Architecture Reload File
  • Architectural Read File

Questão 56

Questão
What is a ROB?
Responda
  • Reorder Buffer
  • Read Only Buffer
  • Reload Buffer
  • Recall Buffer

Questão 57

Questão
What is a FSB?
Responda
  • Finished Store Buffer
  • Finished Stack Buffer
  • Finished Stall Buffer
  • Finished Star Buffer

Questão 58

Questão
What is a PRF?
Responda
  • Physical Register File
  • Pending Register File
  • Pipeline Register File
  • Pure Register File

Questão 59

Questão
What is a SB?
Responda
  • Scoreboard
  • Scorebased
  • Scaleboard
  • Scalebit

Questão 60

Questão
How many stages used in Superscalar (Pipeline)?
Responda
  • 5
  • 4
  • 6

Questão 61

Questão
What is about Superscalar means “F-D-X-M-W”?
Responda
  • Fetch, Decode, Execute, Memory, Writeback
  • Fetch, Decode, Instruct, Map, Write
  • Fetch, Decode, Excite, Memory, Write
  • Fetch, Decode, Except, Map, Writeback

Questão 62

Questão
Speculating on Exceptions “Prediction mechanism” is -
Responda
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
  • Only write architectural state at commit point, so can throw away partially executed instructions after exception
  • none

Questão 63

Questão
Speculating on Exceptions “Check prediction mechanism” is -
Responda
  • Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • The way in which an object is accessed by a subject
  • none

Questão 64

Questão
Speculating on Exceptions “Recovery mechanism” is -
Responda
  • Only write architectural state at commit point, so can throw away partially executed instructions after exception
  • Exceptions are rare, so simply predicting no exceptions is very accurate
  • An entity capable of accessing objects
  • none

Questão 65

Questão
What is a RT?
Responda
  • Rename Table
  • Recall Table
  • Relocate Table
  • Remove Table

Questão 66

Questão
What is a FL?
Responda
  • Free List
  • Free Last
  • Free Leg
  • Free Launch

Questão 67

Questão
What is an IQ?
Responda
  • Issue Queue
  • Internal Queue
  • Interrupt Queue
  • Instruction Queue

Questão 68

Questão
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Responda
  • Width and Lifetime
  • Width and Height
  • Time and Cycle
  • Length and Addition

Questão 69

Questão
Out-of-Order Control Complexity MIPS R10000 which element is in Control Logic?
Responda
  • Register name
  • Instruction cache
  • Data tags
  • Data cache

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