The three main parts of the CPU include: [blank_start]the control unit[blank_end] (CU), [blank_start]the arithmetic and logic unit[blank_end] (ALU) and the [blank_start]cache[blank_end].
Responda
cache
the arithmetic and logic unit
the control unit
Questão 4
Questão
The control unit controls what the user can and cannot access
Responda
True
False
Questão 5
Questão
The cache is very fast memory in the CPU. Recently used applications are stored here so they are quick to access.
Responda
True
False
Questão 6
Questão
The ALU does all of the calculations. The accumulator is stored here
Responda
True
False
Questão 7
Questão
The [blank_start]program counter[blank_end] (PC) holds the [blank_start]memory address[blank_end] of the instruction for each cycle. The accumulator ([blank_start]ACC[blank_end]) stores results of the [blank_start]calculations[blank_end] in the ALU. The Memory Address Register (MAR) stores the any memory address for [blank_start]the next instruction[blank_end] to be carried out by the CPU. The Memory Data Register (MDR) stores data or instructions that have been [blank_start]fetched or waiting to be written[blank_end] to memory.
Responda
program counter
personal computer
pipe cable
number of programs
memory address
name
ACC
ACM
ACUMLTR
decoding
calculations
fetching
executing
all the instructions
the previous instruction
the next instruction
read and waiting to be written
decoded or waiting to be fetched
fetched or waiting to be written
Questão 8
Questão
The fetch in the FDE cycle does:
Responda
Copy memory addresses from PC to MAR
Increments the program counter to the address of the next instruction
Copies the instruction stored in the MAR address to the MDR
Questão 9
Questão
The decode in the FDE cycle does:
Responda
translates the instruction in the MDR
decodes the instruction in the MDR
CU preps for the next step
Questão 10
Questão
The execute in the FDE cycle performs the instruction
Responda
True
False
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