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CPSC313 Midterm Sample

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For when life gives you all the lemons
Zim Brightwood
Quiz by Zim Brightwood, updated more than 1 year ago
Zim Brightwood
Created by Zim Brightwood about 8 years ago
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Resource summary

Question 1

Question
1a) The classic RISC pipeline consists of 5 stages, what are they?
Answer
  • Fetch, Decode, Execute, Memory, Write back
  • Fetch, Register, Execute, Memory, Write back
  • Load, Register, Execute, Memory, Write-read
  • Fetch, Register, Execute, Memory, Load-use
  • Load, Register, Execute, Memory, Control

Question 2

Question
1b) Fetch is responsible for which actions? Check all that apply.
Answer
  • Use pc to read next instruction from memory into instruction register
  • Determine instruction length and extract pieces of instruction
  • Advance the pc to the address of next instruction in sequence
  • Read values from register file
  • Update the pc for taken jump instructions

Question 3

Question
1c) Which of the following is a decode action?
Answer
  • read values from register
  • determine instruction length and extract pieces of instruction
  • access main memory
  • decode the difficulty of this course into a binary representation of tears and not tears

Question 4

Question
1d) Which of the following is an execute stage action?
Answer
  • perform ALU operations and determine whether jumps are taken
  • set the pc for taken jumps
  • access main memory
  • cry profusely into a bowl of alphabits hoping they'll arrange themselves into the proper values for the next stage

Question 5

Question
1e) Which of the following is a memory stage action?
Answer
  • access main memory, duhhhhhhhhhh
  • access main memory and write the values back to the register file, duhhhhhhhhhhh
  • when in doubt choose c
  • advance the pc to the next memory address in the sequence

Question 6

Question
1f) Which of the following is a write back stage action?
Answer
  • write values back to register file
  • write values back to main memory
  • write values back to the pc
  • forge your computer science degree when failing this course leads you into months of crippling depression

Question 7

Question
2a) Why is the memory stage after the execute stage? Include a Y86 instruction that could not be implemented if you reversed the order.
Answer
  • Execute needs to perform address calculations. mrmovl could not use base plus displacement addressing
  • Execute needs to perform math on register values. None of the op instructions would work (i.e. addl)
  • Memory needs to write a value from memory into a register. mrmovl would not work if the order was reversed.
  • Memory needs to read from memory in order for execute to work properly. ret would not work if the order was reversed.

Question 8

Question
2b) Why is the execute stage after the decode stage? Include a Y86 instruction that could not be implemented if you reversed the order.
Answer
  • Execute needs to be able to perform math on register values. If the order were reversed, none of the op instructions would work (i.e. addl)
  • Execute needs to perform address calculations. If the order were reversed, mrmovl would not work.
  • Decode needs to write a value from memory into a register. mrmovl would no longer work if the order was reversed.
  • Decode needs to read the values before execute stage to avoid stalling. popl would no longer work if the order was reversed.

Question 9

Question
2c) Why is the write-back stage after the memory stage? Include a Y86 instruction that could not be implemented if you reversed the order.
Answer
  • Memory needs to perform math on memory values. In the reverse order, none of the op instructions would work (i.e. addl)
  • Memory needs to perform address calculations. In the reverse order, mrmovl and rmmovl would not work.
  • Write back needs to be able to write a value from memory into a register. In the reverse order, mrmovl would not work.

Question 10

Question
3a) RISC instruction sets do not allow ALU operations to read from memory. Explain how the structure of the pipeline leads this restriction.
Answer
  • Since M comes after E, by the time we read the value from memory, it's too late.
  • Since M comes before E, by the time we read the value from memory, it's too late.
  • Since E comes after M, by the time we read the value from memory, it's too late.

Question 11

Question
3b) Describe how the pipeline could be modified to lift this restriction. You may not change the number of pipeline stages or their basic function. Your revised pipeline does not need to be able to implement every Y86 instruction (in fact it would not be able to) but it must be able to execute instructions like: addl (%eax), %ebx # r[ebx] = r[ebx] + m[r[eax]]
Answer
  • Swap the order of E and M
  • Allow for M to forward data back to E
  • Stall E until M has the correct data

Question 12

Question
3c) This revised pipeline must place some restrictions on the revised ISA that it implements. One of the impacts is on mrmovl and rmmovl. Describe the problem and modify the instructions so that they will work with the new pipeline. Note that the revised versions need not be as powerful as the original ones, but they must still load and store between memory and a register.
Answer
  • We wouldn't be able to handle base plus addressing because E would come after M. To solve this, we simply eliminate base plus addressing
  • Memory access is rendered useless. To solve this, we simply eliminate the memory stage.
  • The write back stage would no longer be able to determine the correct register to move data to. To solve this, we would simply add another stage input to account for that lost addressing.

Question 13

Question
Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps, 42 ps, 75 ps, 50 ps and 18 ps. What is the maximum clock rate (i.e., fastest) acceptable for this pipeline? [blank_start]1 cycle / 75ps = 1000/75 Ghz[blank_end]
Answer
  • 1 cycle / 75ps = 1000/75 Ghz
  • 1 cycle / 34ps = 1000/34 Ghz
  • 1 cycle / 42ps = 1000/42 Ghz
  • 1 cycle / 50ps = 1000/50 Ghz
  • 1 cycle / 18ps = 1000/18 Ghz

Question 14

Question
Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps, 42 ps, 75 ps, 50 ps and 18 ps. What is the maximum throughput of this pipeline? [blank_start]1/75 instructions per picosecond[blank_end]
Answer
  • 1/75 instructions per picosecond
  • 1/34 instructions per picosecond
  • 1/42 instructions per picosecond
  • 1/50 instructions per picosecond
  • 1/18 instructions per picosecond

Question 15

Question
4c) Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps, 42 ps, 75 ps, 50 ps and 18 ps. What, if anything, might cause the actual throughput of programs to be lower than this maximum?
Answer
  • pipeline bubbles
  • nothing would cause that, the maximum is actually also the minimum
  • jumps and returns
  • stack depletion

Question 16

Question
Consider the following five-stage pipeline with stage delays (including overheads) of 34 ps, 42 ps, 75 ps, 50 ps and 18 ps. What is the minimum instructions latency of this pipeline? [blank_start]75ps + 75ps + 75ps + 75ps + 75ps[blank_end]
Answer
  • 75ps + 75ps + 75ps + 75ps + 75ps
  • 34ps + 42ps + 50ps + 75ps + 18ps
  • 18ps + 18ps + 18ps + 18ps + 18ps

Question 17

Question
5a) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax List all of the output dependencies present in this code.
Answer
  • 0 and 2 on %ebx
  • 0 and 1 on %eax
  • 0 and 3 on %ebx
  • 1 and 2 on %ebx
  • 1 and 3 on %eax
  • 2 and 3 on %ebx

Question 18

Question
5a) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax List all of the anti dependencies present in this code.
Answer
  • 0 and 1 on %eax
  • 0 and 2 on %ebx
  • 0 and 3 on %ebx
  • 1 and 2 on %ebx
  • 1 and 3 on %eax
  • 2 and 3 on %ebx

Question 19

Question
5a) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax List all of the causal dependencies present in this code.
Answer
  • 0 and 1 on %eax
  • 0 and 2 on %ebx
  • 0 and 3 on %eax
  • 1 and 2 on %ebx
  • 1 and 3 on %eax
  • 2 and 3 on %ebx

Question 20

Question
5b) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax List all of the data hazards present in this code for the Y86, five stage pipeline
Answer
  • All the dependencies
  • All the causal dependencies
  • All the output dependencies
  • All the anti dependencies
  • Just the causal and output dependencies
  • Just the causal and anti dependencies
  • Just the anti and output dependencies

Question 21

Question
5c) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax For each hazard, indicate the total number of bubbles added by the Pipe-Minus implementation
Answer
  • 2 for dependency between 0 and 2 on %ebx
  • 1 for dependency between 0 and 2 on %ebx
  • 3 for dependency between 0 and 2 on %ebx
  • 0 for dependency between 1 and 3 on %eax
  • 1 for dependency between 1 and 3 on %eax
  • 2 for dependency between 1 and 3 on %eax
  • 0 for dependency between 0 and 2 on %ebx
  • 3 for dependency between 1 and 3 on %eax
  • 3 for dependency between 2 and 3 on %ebx
  • 2 for dependency between 2 and 3 on %ebx

Question 22

Question
5d) Consider the following piece of Y86 assembly code: [0] addl %eax, %ebx [1] irmovl $1, %eax [2] mrmovl %(ebx), %ebx [3] addl %ebx, %eax For each hazard, indicate the total number of bubbles added by the Pipe implementation
Answer
  • 1 for dependency between 2 and 3 on %ebx
  • 2 for dependency between 2 and 3 on %ebx
  • 3 for dependency between 2 and 3 on %ebx
  • 0 for dependency between 2 and 3 on %ebx

Question 23

Question
Describe the implementation of the following new instruction for Y86 Seq as you did in Homework 2. This instruction is similar to mrmovl except that it adds 4 to rB and does not have a static-displacement operand. It would be useful, for example, for iterating over an array of integers. Syntax: mrmovincl (rB), rA Semantics: r[rA] <= m[r[rB]] r[rB] <= r[rB] + 4 Memory Layout: | 5 | F | rA | rB | Describe each stage using a relaxed syntax similar as shown below. The Fetch and PC Update stages are complete. List only the code that would be added for this instruction. Fetch: f.iCd = m[F.pc] >> 4 f.iFn = m[F.pc] & 0xf f.rA = m[F.pc+1] >> 4 f.rB = m[F.pc+1] & 0xf f.valP = F.pc + 2 Decode: d.srcA = [blank_start]R_NONE[blank_end] d.srcB = [blank_start]D.rB[blank_end] d.dstE = D.rB d.dstM = [blank_start]D.rA[blank_end] d.valB = [blank_start]r[d.srcB][blank_end] Execute: e.aluA = 4 e.aluB = [blank_start]E.valB[blank_end] e.aluFun = [blank_start]A_ADD[blank_end] e.valE = [blank_start]4 + E.valB[blank_end] Memory: m.valM = [blank_start]m4[M.valB][blank_end] Write Back: r[W.dstE] = [blank_start]W.valE[blank_end] r[W.dstM] = [blank_start]W.valM[blank_end] PC Update (pseudo stage): w.pc = W.valP
Answer
  • R_NONE
  • D.rB
  • D.rA
  • r[d.srcB]
  • E.valB
  • A_ADD
  • A_SUB
  • A_INC
  • 4 + E.valB
  • m4[M.valB]
  • m4[M.srcB]
  • W.valE
  • W.valM
  • R_ADD
  • R_SUB

Question 24

Question
Write Y86 assembly code that computes the sum of an array of integers where the address of the array is stored in %ebx and the length of the array is in %ecx. Place the sum in %eax. irmovl $0, [blank_start]%eax[blank_end] #SET SUM TO 0 irmovl $[blank_start]1[blank_end], %edi #HOW MUCH WILL THE LENGTH DECREMENT BY AS YOU ITERATE? irmovl $[blank_start]4[blank_end], %esi #AN ARRAY OF INTEGERS HAS ELEMENTS WITH A SIZE OF? [blank_start]andl[blank_end] %ecx, %ecx #IS THE LENGTH OF THE ARRAY 0? jle L1 L0: [blank_start]mrmovl[blank_end] [blank_start](%ebx)[blank_end], %edx #STORE ADDRESS OF ARRAY INTO %edx addl [blank_start]%edx[blank_end], %eax #ADD VALUE OF ELEMENT IN THE ARRAY TO SUM addl [blank_start]%esi[blank_end], %ebx #INCREMENT THE ARRAY POINTER subl [blank_start]%edi[blank_end], %ecx #DECREMENT THE LENGTH OF THE ARRAY [blank_start]jg[blank_end] L0 #CHECK IF LENGTH IS STILL GREATER THAN ZERO L1:
Answer
  • %eax
  • 1
  • 2
  • 3
  • 4
  • 5
  • andl
  • mrmovl
  • rmmovl
  • rrmovl
  • (%ebx)
  • %ebx
  • %edx
  • %esi
  • %edi
  • jg
  • jge
  • jle
  • jl

Question 25

Question
8a) What is spatial locality and why is it important?
Answer
  • Spatial locality exists when memory accesses are clustered together to nearby memory addresses
  • Caches exploit spatial locality by storing data in multi-byte blocks.
  • Spatial locality exists when the same memory location is accessed repeatedly.
  • Caches exploit spatial locality by retaining recently accessed blocks in the cache.
  • Spatial locality exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
  • Pipelined (and super-scalar) processor architectures exploit spatial locality.
  • Spatial locality exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
  • Multi-core processors (and hyper-threading) exploit spatial locality.

Question 26

Question
8b) What is temporal locality and why is it important?
Answer
  • Temporal locality exists when memory accesses are clustered together to nearby memory addresses.
  • Caches exploit temporal locality by storing data in multi-byte blocks.
  • Temporal locality exists when the same memory location is accessed repeatedly.
  • Caches exploit temporal locality by retaining recently accessed blocks in the cache.
  • Temporal locality exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
  • Pipelined (and super-scalar) processor architectures exploit temporal locality.
  • Temporal locality exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
  • Multi-core processors (and hyper-threading) exploit temporal locality.

Question 27

Question
8c) What is instruction-level parallelism and why is it important?
Answer
  • Instruction-level parallelism exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
  • Pipelined (and super-scalar) processor architectures exploit instruction-level parallelism.
  • Instruction-level parallelism exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
  • Multi-core processors (and hyper-threading) exploit instruction-level parallelism.
  • Instruction-level parallelism exists when the same memory location is accessed repeatedly.
  • Caches exploit instruction-level parallelism by storing data in multi-byte blocks.
  • Instruction-level parallelism exists when memory accesses are clustered together to nearby memory addresses.
  • Caches exploit instruction-level paralellism by retaining recently accessed blocks in the cache.

Question 28

Question
8d) What is thread-level parallelism and why is it important?
Answer
  • Thread-level parallelism exists when programs explicitly indicate that threads of execution can be executed in parallel by either directly or indirectly creating multiple threads that can execute con-currently.
  • Multi-core processors (and hyper-threading) exploit thread-level parallelism.
  • Thread-level parallelism exists between a pair of instructions when there are no dependencies between them and thus their execution order does not matter.
  • Pipelined (and super-scalar) processor architectures exploit thread-level parallelism.
  • Thread-level parallelism exists when the same memory location is accessed repeatedly.
  • Caches exploit thread-level parallelism by retaining recently accessed blocks in the cache.
  • Caches exploit thread-level parallelism by storing data in multi-byte blocks.
  • Thread-level parallelism exists when memory accesses are clustered together to nearby memory addresses.

Question 29

Question
Polymorphic dispatch common to object-oriented languages like Java is implemented using a double-indirect call instruction that reads an address from memory and then jumps to it. Explain why it is challenging to implement such an instruction without stalling in a pipelined processor.
Answer
  • The address of the next instruction to execute after the call is not known to the pipeline until the call instruction exits the memory stage and so predicting which instructions should be F, D, and E at this point is impossible without retaining execution history.
  • If the predPC is overwritten with the address of a call at a stage earlier than memory, the instructions already in the pipeline will bubble.
  • Couldn't we all just down a bottle of bleach instead of do this midterm?

Question 30

Question
Consider the following instruction-execution frequencies for a program running on the standard Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory. 7% read register immediately after an instruction writes into that register a value it reads from memory 6% read register immediately after an instruction writes into that register a value computed in Execute 12% conditional jump that is taken 8% conditional jump that is not taken 5% call 5% ret 57% the remaining introduce no bubbles What is the average cycles per instruction for this execution?
Answer
  • CPI = 1 + 0.07 + 0.08 * 2 + 0.05 * 3 = 1.38 Because load-use causes 1 bubble, not taken penalties cause 2 bubbles, and ret instructions cause 3 bubbles
  • CPI = 1 + 0.07 * 2 + 0.08 * 3 + 0.05 = 1.43 Because load-use causes 2 bubbles, not taken penalties cause 3 bubbles, and ret instructions cause 1 bubble
  • CPI = 1 + 0.06 * 2 + 0.12 * 3 + 0.05 = 1.41 Because forwarding causes 2 bubbles, taken penalties cause 3 bubbles, and call instructions cause 1 bubble
  • CPI = 1 + 0.06 + 0.12 * 2 + 0.05 * 3 = 1.45 Because forwarding causes 1 bubble, taken penalties cause 2 bubbles, and call instructions cause 3 bubbles

Question 31

Question
Consider the following instruction-execution frequencies for a program running on the standard Y86 Pipe processor. The table shows, for example, that 7% of all instructions executed read the value of a register immediately after the preceding instruction modified that register by writing into it a value that came from memory. 7% read register immediately after an instruction writes into that register a value it reads from memory 6% read register immediately after an instruction writes into that register a value computed in Execute 12% conditional jump that is taken 8% conditional jump that is not taken 5% call 5% ret 57% the remaining introduce no bubbles What is the throughput of this execution on a 3-Ghz processor (ie 3*10^9 cycles per second)? (You may go back one question to see what you chose for the answer.
Answer
  • (3*10^9 / 1.38) instructions per second
  • (3*10^9 / 1.41) instructions per seconds
  • (3*10^9 / 1.43) instructions per seconds
  • (3*10^9 / 1.45) instructions per seconds
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