Zusammenfassung der Ressource
ICT2104 Chapter 4: Interrupts
- CPU Processing Stages
- RESET State: CPU and internal peripheral modules are initialised and stopped
- Exception-Processing State: Transient state that occurs when CPU alters normal processing flow due to exception source
- Program Execution State; CPU executes program instructions in sequence
- Bus-Released State: Occurs when bus has been released in response to bus request from a bus master; CPU halts operations
- Program Stop State: Power-down state which CPU stops operating
- Reset and Interrupts
- Program Execution
- PC: Points to next instruction to be executed
- SR: Subsequent instruction make use of altered values of SR to carry out branch condition
- SP: Storing of information that cannot be over-written within ISR
- RESET: Allows fetching the first instruction to be executed after a power-up
- Other Reset Triggers
- Only triggers when button is released
- Power-On Reset
- Is a NMI
- Reset Signal must be active for at least 2us
- IVT and Priority
- Reset Address
- Fixed Vector
- Auto-Vectored
- MSP430 port interrupt registers
- Types
- NMI: Cannot be disabled by GIE; Used for high priority events
- MI: GIE must be set, can be switched off by software
- Interruptible Ports: Port 1 & Port 2
- PxIFG: Interrupt Flag
- Bit 1: Interrupt pending
- Bit 0: No interrupt pending
- PxIE: Interrupt Enable
- Bit 1: Interrupt enabled
- Bit 0: Interrupt disabled
- PxIES: Interrupt Edge Select
- Bit 1: Falling Edge
- Bit 0: Rising Edge
- #pragma vector = PORTx_VECTOR
- During interrupt event
- PC points to next instruction and is pushed with SR to stack
- SR is cleared (except SCG0) and GIE flag
- RETI returns to original program flow, pops SR and PC
- ISR processing time should be < interrupt's request time interval
- To avoid stack overflow, collapsing program
- Interrupt Latency: Time between event beginning and ISR execution
- Interrupt identification and priority determination
- Identification Methods
- Non-vectored
- Unable to identify which device directly
- CPU has to check which device within ISR
- Vectored-Based
- Auto-Vectored
- Vector number is predefined by assigning an interrupt to a vector number
- Generated internally by CPU
- Only one IRQ line, no acknowledgement
- Only 1 interrupt / IRQ line
- Full-Vectored
- Can be supplied by device itself
- Provided by device
- IRQ + IACK lines: Handshake logic
- Flexible as device can send different #
- Can have > 1 IRQ line
- Each interrupt is uniquely identified with a different vector number
- More flexible in providing priority and masking of bits
- Requires a lot of hardware resources to resolve additional issues (i.e. masking)
- Priority Handling
- Daisy Chain
- The closer it is to CPU, the higher the priority
- Hardwired, difficult to balance services among devices
- Interrupt Controller
- Programmable support peripheral, allows handling of requests from multiple devices
- Flexible in terms of priority management
- Interrupt processing stages and latency
- Stages
- 1. Complete any currently executing instructions
- 2. Push PC to stack
- 3. Push SR to stack
- 4. Select highest priority interrupt if multiple interrupts occured
- 5. IFG resets automatically on single-source flag. Otherwise, IFG remain set.
- 6. Clear all bits of SR (except SCG0) and GIE.
- 7. Load content of interrupt vector into PC; continues ISR.
- Latency
- At least 6 clock cycles before ISR executes (see stages)
- RETI requires 5 cycles
- 1. Pop SR and GIE from stack
- 2. Pop PC from stack and continues execution from where it was interrupted
- Interrupt driven I/O
- Maximum interrupt handler execution time permitted: Time between each interrupt
- Multiple interrupts and interrupt nesting