Kopieren und bearbeiten

PCA_Final_Exam_New_Questions

Beschreibung

This is zalupa ebanaya.
Good Guy Beket
Quiz von Good Guy Beket, aktualisiert more than 1 year ago
Good Guy Beket
Erstellt von Good Guy Beket vor mehr als 6 Jahre
676
18
0

Zusammenfassung der Ressource

Frage 1

Frage
In 32-bit addressing mode, address field is either 1 byte or?
Antworten
  • 4 bytes
  • 2 bytes
  • 6 bytes

Frage 2

Frage
If a block can be placed at every location in cache, this cache is said to be?
Antworten
  • Fully associative
  • Directly mapped
  • Indirectly mapped

Frage 3

Frage
Information when is written in cache, both to block in cache and block present in lower-level memory, refers to?
Antworten
  • Write-through
  • Write-back
  • Miss rate

Frage 4

Frage
Average access time of memory for having memory-hierarchy performance is given as?
Antworten
  • Average memory access time = Hit time - Miss rate
  • Average memory access time = Hit time + (miss rate and miss penalty)
  • Average memory access time = Hit time + Miss rate - Miss penalty

Frage 5

Frage
As segment or a page is normally used for block, page-fault and address-fault is used for:
Antworten
  • Hit
  • Miss
  • Cache
  • Stack

Frage 6

Frage
Virtual memory producing virtual-addresses, are translated by:
Antworten
  • Logical addresses
  • Physical addresses
  • Local addresses
  • All above

Frage 7

Frage
Per memory reference, miss-rate can be turned into per instruction misses rate by
Antworten
  • Miss rate= Memory accesses* instructions
  • Miss rate= Memory accesses/ instructions
  • Miss rate= Memory accesses-instructions
  • Miss rate= Memory accesses+ instructions

Frage 8

Frage
Cutting of physical-memory into form of blocks and allocating them to different processes, stated technique is known as
Antworten
  • Read back
  • Cache miss
  • Virtual memory
  • Cache hit

Frage 9

Frage
For reducing frequency on replacement of write-back blocks, commonly used feature, is known as:
Antworten
  • Hit miss
  • Index field
  • Dirty bit
  • Write-through

Frage 10

Frage
If cache is not able for containing all blocks needed while execution, miss is then known as
Antworten
  • Hit miss
  • Cache hit
  • Cache miss (capacity miss)
  • Hit rate

Frage 11

Frage
For completing programmer's desire for unlimited quick memory, suggested economical solution was:
Antworten
  • Memory hierarchy
  • Temporal locality
  • Spatial locality

Frage 12

Frage
An instruction that does no operation for changing state is known as
Antworten
  • Nope
  • No
  • NOP

Frage 13

Frage
Set of instructions examined as candidates for potential execution is called the
Antworten
  • Frame
  • Cube
  • Window

Frage 14

Frage
Term 'computer architecture' is sometimes referred only to:
Antworten
  • Instruction set design
  • Circuit design
  • Hardware design

Frage 15

Frage
General categories of instructions' operation are
Antworten
  • Data transfer
  • Arithmetic logical
  • floating point
  • All above

Frage 16

Frage
The effectiveness of the cache memory is based on the property of:
Antworten
  • Locality of reference
  • Memory localization
  • Memory size

Frage 17

Frage
The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______.
Antworten
  • Level 2 cache
  • Level 1 cache
  • Registers

Frage 18

Frage
The last on the hierarchy scale of memory devices is ______.
Antworten
  • Main memory
  • Branch
  • Secondary memory

Frage 19

Frage
A common measure of performance is
Antworten
  • Price/performance ratio.
  • Performance/price ratio
  • Operation/price ratio.

Frage 20

Frage
The number successful accesses to memory stated as a fraction is called as _____
Antworten
  • Miss rate
  • Hit rate
  • Access rate

Frage 21

Frage
With respect to changing among states of accomplishment and interruption, a measure of continuous service-accomplishment, is known as:
Antworten
  • Scalability
  • Module availability
  • Module reliability

Frage 22

Frage
From a reference initial instant, a measure of service accomplishment, is known as:
Antworten
  • Module reliability
  • Hardware
  • Sector

Frage 23

Frage
To initialize any port as an output port what value is to be given to it?
Antworten
  • 0xFF
  • 0x00
  • 0x01
  • A port is by default an output port

Frage 24

Frage
In AVR, which registers are there for the I/O programming of ports?
Antworten
  • all above
  • PORT
  • PIN
  • DDR

Frage 25

Frage
The data will not go from the port registers to the pin unless:
Antworten
  • DDR register of that port is set to 0
  • DDR register of that port is set to 1
  • PORT register of that port is set to 0

Frage 26

Frage
What is the file extension that is loaded in a micro controller for executing any instruction?
Antworten
  • .doc
  • .hex
  • .txt

Frage 27

Frage
What type of coherence misses is - that arise from the communication of data through the cache coherence mechanism?
Antworten
  • True sharing misses
  • False sharing misses

Frage 28

Frage
What type of coherence misses is - that arises from the use of an invalidation based coherence algorithm with a single valid bit per cache block?:
Antworten
  • False sharing misses
  • True sharing misses

Frage 29

Frage
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Shared” in a simple protocol?
Antworten
  • One or more processors have the block cached, and the value in memory is up to date
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • No processor has a copy of the cache block

Frage 30

Frage
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Modified” in a simple protocol?
Antworten
  • No processor has a copy of the cache block
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • One or more processors have the block cached, and the value in memory is up to date

Frage 31

Frage
At Directory-Based Cache Coherence Protocols: The Basics, which state in the following called “Uncached” in a simple protocol?
Antworten
  • No processor has a copy of the cache block
  • Exactly one processor has a copy of the cache block, and it has written the block, so the memory copy is out of date
  • One or more processors have the block cached, and the value in memory is up to date

Frage 32

Frage
In Non-Blocking Caches what does mean “Early restart”?
Antworten
  • Fetch the words in normal order, but as soon as the requested word of the block arrives, send it to the processor and let the processor continue execution
  • Request the missed word first from memory and send it to the processor as soon as it arrives; let the processor continue execution while filling the rest of the words in the block

Frage 33

Frage
What occurs at Instruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Antworten
  • n loop iterations
  • subroutine call
  • vector access

Frage 34

Frage
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
  • subroutine call
  • n loop iterations
  • vector access

Frage 35

Frage
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Antworten
  • subroutine call
  • n loop iterations
  • vector access

Frage 36

Frage
What is kernel process?
Antworten
  • Provide at least two modes, indicating whether the running process is a user process or an operating system process
  • Provide at least five modes, indicating whether the running process is a user process or an operating system process
  • Provide a portion of the processor state that a user process can use but not write
  • None of them

Frage 37

Frage
Which one is NOT concerning to pitfall?
Antworten
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Frage 38

Frage
Which one is concerning to fallacy?
Antworten
  • Predicting cache performance of one program from another
  • Simulating enough instructions to get accurate performance measures of the memory hierarchy
  • Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
  • Over emphasizing memory bandwidth in DRAMs

Frage 39

Frage
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Antworten
  • Speculative operations that don’t cause exceptions
  • Hardware to check pointer hazards

Frage 40

Frage
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Antworten
  • Hardware to check pointer hazards
  • Speculative operations that don’t cause exceptions

Frage 41

Frage
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Antworten
  • Allow one instruction to branch multiple directions
  • Speculative operations that don’t cause exceptions

Frage 42

Frage
In Multilevel Caches “Local miss rate” equals =
Antworten
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses
  • misses in cache / number of instructions

Frage 43

Frage
In Multilevel Caches “Global miss rate” equals =
Antworten
  • misses in cache / CPU memory accesses
  • misses in cache / accesses to cache
  • misses in cache / number of instructions

Frage 44

Frage
In Multilevel Caches “Misses per instruction” equals =
Antworten
  • misses in cache / number of instructions
  • misses in cache / accesses to cache
  • misses in cache / CPU memory accesses

Frage 45

Frage
The time between the start and the completion of an event ,such as milliseconds for a disk access is...
Antworten
  • latency
  • bandwidth
  • throughput
  • performance

Frage 46

Frage
Total amount of work done in a given time , such as megabytes per second for disk transfer...
Antworten
  • bandwidth (throughput)
  • latency
  • performance

Frage 47

Frage
Products that are sold by multiple vendors in large volumes and are essentially identical
Antworten
  • commodities
  • boxes
  • folders
  • files

Frage 48

Frage
Integrated circuit processes are characterized by the:
Antworten
  • feature size
  • permanent size n
  • complex size
  • fixed size

Frage 49

Frage
Manufacturing costs that decrease over time are ____
Antworten
  • the learning curve
  • the cycled line
  • the regular option
  • the final loop

Frage 50

Frage
Volume is a ________ key factor in determining cost.
Antworten
  • second
  • first
  • fifth
  • third

Frage 51

Frage
The most companies spend only ____________ of their income on R&D, which includes all engineering.
Antworten
  • 4% to 12%
  • 15% to 30%
  • 1% to 17%
  • 30% to 48%

Frage 52

Frage
Desktop benchmarks divide into __ broad classes:
Antworten
  • two
  • three
  • four
  • five

Frage 53

Frage
A widely held rule of thumb is that a program spends __ of its execution time in only __ of the code.
Antworten
  • 90% 10%
  • 50% 50%
  • 70% 30%
  • 89% 11%

Frage 54

Frage
(Performance for entire task using the enhancement when possible) / (Performance for entire task without using the enhancement) is equals to:
Antworten
  • Speedup
  • Efficiency
  • Probability
  • Ration

Frage 55

Frage
Which of the following descriptions corresponds to static power?
Antworten
  • Grows proportionally to the transistor count (whether or not the transistors are switching)
  • Proportional to the product of the number of switching transistors and the switching rate Probability
  • Proportional to the product of the number of switching transistors and the switching rate
  • All of the above

Frage 56

Frage
If we want to sustain four instructions per clock
Antworten
  • We must fetch more, issue more, and initiate execution on more than four instructions
  • We must fetch less, issue more, and initiate execution on more than two instructions
  • We must fetch more, issue less, and initiate execution on more than three instructions
  • We must fetch more, issue more, and initiate execution on less than five instructions

Frage 57

Frage
What is a hash table?
Antworten
  • Popular data structure for organizing a large collection of data items so that one can quickly answer questions
  • Popular data structure for updating large collections, so that one can hardly answer questions
  • Popular tables for organizing a large collection of data structure
  • Popular data structure for deletingsmall collections of data items so that one can hardly answer questions

Frage 58

Frage
How this process called: “Operations execute as soon as their operands are available”
Antworten
  • data flow execution
  • instruction execution
  • data control execution
  • instruction field execution

Frage 59

Frage
For what the reorder buffer is used :
Antworten
  • To pass results among instructions that may be speculated.
  • To pass parameters through instructions that may be speculated
  • To get additional registers in the same way as the reservation stations
  • To control registers

Frage 60

Frage
Which one is not the major flavor of Multiple-issue processors:
Antworten
  • statistically superscalar processors
  • dynamically scheduled superscalar processors
  • statically scheduled superscalar processors
  • VLIW (very long instruction word) processors

Frage 61

Frage
Examples of superscalar(static):
Antworten
  • MIPS and ARM
  • Pentium 4, MIPS R12K, IBM, Power5
  • Itanium
  • TI C6x

Frage 62

Frage
Examples of superscalar(dynamic) :
Antworten
  • None at the present
  • Pentium 4, MIPS R12K, IBM, Power5
  • MIPS and ARM
  • TI C6x

Frage 63

Frage
Examples of VLIW processor:
Antworten
  • TI C6x
  • MIPS and ARM
  • Itanium
  • Pentium 4, MIPS R12K, IBM, Power5

Frage 64

Frage
Which is not the function of integrated instruction fetch unit:
Antworten
  • Instruction memory commit
  • Integrated branch prediction
  • Instruction prefetch
  • Instruction memory access and buffering

Frage 65

Frage
In the memory hierarchy, as the speed of operation increases the memory size also increases:
Antworten
  • True
  • False

Frage 66

Frage
At VLIW by “performance and loop iteration” which time is longer?
Antworten
  • Loop Unrolled
  • Software Pipelined

Frage 67

Frage
At VLIW by “performance and loop iteration” which time is shorter?
Antworten
  • Software Pipelined
  • Loop Unrolled

Frage 68

Frage
What is a topology in interconnection networks?
Antworten
  • It indicates how the nodes a network are organised
  • It is the minimum distance between the farthest nodes in a network
  • Number of edges connected with a node is called node degree

Frage 69

Frage
What is a Network Diameter?
Antworten
  • It is the minimum distance between the farthest nodes in a network
  • It indicates how the nodes a network are organized
  • Number of edges connected with a node is called node degree

Frage 70

Frage
What is a Node degree?
Antworten
  • Number of edges connected with a node
  • It indicates how the nodes a network are organized
  • It is the minimum distance between the farthest nodes in a network

Frage 71

Frage
What is a Bisection Bandwidth?
Antworten
  • Number of edges required to be cut to divide a network into two halves
  • It indicates how the nodes a network are organized
  • It is the minimum distance between the farthest nodes in a network

Frage 72

Frage
What is Latency?
Antworten
  • It indicates how the nodes a network are organized
  • It is the delay in transferring the message between two nodes
  • It is the minimum distance between the farthest nodes in a network

Frage 73

Frage
What is a Hardware Cost?
Antworten
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed established the path between the source and the destination
  • It refers to the cost involved in the implementation of an interconnection network
  • It is an indicative measure of the message carrying capacity of a network

Frage 74

Frage
What is a Blocking and Non-Blocking network?
Antworten
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed establishe the path between the source and the destination
  • In non-blocking networks the route from any free input node to any free output node can always be provided
  • It is an indicative measure of the message carrying capacity of a network

Frage 75

Frage
Design issue of interconnection network
Antworten
  • Software Cost
  • Hardware Cost
  • RLP
  • Symmetry of the network

Frage 76

Frage
What is a Data transfer time?
Antworten
  • It indicates how the nodes a network are organized
  • The data routing functions are the functions which when executed established the path between the source and the destination
  • How long does it take for a message to reach to another processor
  • It is an indicative measure of the message carrying capacity of a network

Frage 77

Frage
Select non-blocking interconnection network
Antworten
  • Linear Array
  • Cube
  • CrossBar

Frage 78

Frage
A modified version of the tree interconnection network
Antworten
  • Fat tree
  • Cube
  • Linear Array

Frage 79

Frage
An interconnection network is a type of pipelined array architecture and it is designed for multidimensional flow of data
Antworten
  • Systolic Array
  • Cube
  • Linear Array

Frage 80

Frage
A _____________ interconnection network is an extension of cube network
Antworten
  • Hyper Cube
  • Cube
  • Linear Array

Frage 81

Frage
In computer architecture, __________________ is the ability of a central processing unit (CPU) or a single core in a multi-core processor to execute multiple processes or threads concurrently, appropriately supported by the operating system.
Antworten
  • Multithreading
  • Computing
  • Array processing

Frage 82

Frage
Single Instruction, Single Data (SISD):
Antworten
  • Only one instruction stream is being acted on by the CPU during any one clock cycle
  • A type of parallel computer
  • Currently, the most common type of parallel computer - most modern supercomputers fall into this category

Frage 83

Frage
Pipelining …
Antworten
  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line
  • A logically discrete section of computational work
  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory

Frage 84

Frage
Shared Memory…
Antworten
  • From a strictly hardware point of view, describes a computer architecture where all processors have direct (usually bus based) access to common physical memory
  • A logically discrete section of computational work
  • Breaking a task into steps performed by different processor units, with inputs streaming through, much like an assembly line

Frage 85

Frage
What is a RISC computers?
Antworten
  • Reduced Instruction Set Computer
  • Rational Interruptible Security Computer
  • Research Interconnect Several Computer

Frage 86

Frage
When single-processor performance improvement has dropped?
Antworten
  • 2003
  • 2004
  • 2002

Frage 87

Frage
How much in percentage single-processor performance improvement has dropped to less than?
Antworten
  • 22%
  • 11%
  • 33%

Frage 88

Frage
How many classes of computers classified?
Antworten
  • 3
  • 5
  • 7

Frage 89

Frage
What is the PMD in computer classes?
Antworten
  • Percentage map device
  • Powerful markup distance
  • Peak maze development
  • Personal mobile device

Frage 90

Frage
What is the Thread Level Parallelism?
Antworten
  • Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Frage 91

Frage
What is the Request Level Parallelism:
Antworten
  • o Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that allows for interaction among parallel threads.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.

Frage 92

Frage
What is the Instruction Level Parallelism:
Antworten
  • Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at medium levels using ideas like speculative execution
  • Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
  • Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.

Frage 93

Frage
What is the MISD one of the categories of computers?
Antworten
  • Multiple Instructions Streams, Single Data Stream
  • Multiple Instruction Streams, Multiple Data Streams
  • Multiple Instruction Streams, Set Data Stream

Frage 94

Frage
How many elements in Trends of Technology?
Antworten
  • 5
  • 4
  • 6

Frage 95

Frage
How many elements of the Instruction Set Architecture (ISA):
Antworten
  • 7
  • 8

Frage 96

Frage
How many types of dependencies do you know?
Antworten
  • 3
  • 4
  • 5

Frage 97

Frage
How many possible Elements of Data Hazards?
Antworten
  • 3
  • 6
  • 8

Frage 98

Frage
What is the “ISSUE” in Pipelining Basics?
Antworten
  • Decode instructions, check for structural hazard
  • Decode instructions, check for data hazard
  • Decode instructions, check for control hazard

Frage 99

Frage
What is the “Read Operands” in Pipelining Basics?
Antworten
  • Wait until no data hazards, then read operands
  • Wait until no control hazards, then read operands
  • Wait until no structural hazards, then read operands

Frage 100

Frage
How many Optimizations’ in Cache memory Performance?
Antworten
  • 10
  • 8
  • 6

Frage 101

Frage
What is the Compulsory in main categories in Cache Memory?
Antworten
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Frage 102

Frage
What is the Capacity in main categories in Cache Memory?
Antworten
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)
  • first-reference to a block, occur even with infinite cache
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)

Frage 103

Frage
What is the Conflict in main categories in Cache Memory?
Antworten
  • misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
  • first-reference to a block, occur even with infinite cache
  • cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache lines)

Frage 104

Frage
What is the Temporal Locality?
Antworten
  • Exploit by remembering the contents of recently accessed locations
  • Exploit by fetching blocks of data around recently accessed locations

Frage 105

Frage
What is the Spatial Locality?
Antworten
  • Exploit by fetching blocks of data around recently accessed locations
  • Exploit by remembering the contents of recently accessed locations

Frage 106

Frage
What is the Reducing the Hit time?
Antworten
  • Small and simple first-level caches and way-prediction
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Critical word first and merging write buffer

Frage 107

Frage
What is the Increasing cache bandwidth?
Antworten
  • Pipelined caches, multibanked caches, and nonblocking caches
  • Small and simple first-level caches and way-prediction
  • Critical word first and merging write buffer

Frage 108

Frage
What is the Reducing the Miss Penalty?
Antworten
  • Critical word first and merging write buffer
  • Small and simple first-level caches and way-prediction
  • Pipelined caches, multibanked caches, and nonblocking caches

Frage 109

Frage
What is the Reducing the Miss Rate?
Antworten
  • Compiler Optimization
  • Time Optimization
  • Performance Optimization

Frage 110

Frage
Main term of dependability is SLAs?
Antworten
  • Service level agreements
  • Standard level achievement
  • Scale level approach

Frage 111

Frage
Main term of dependability is SLOs?
Antworten
  • Service level objectives
  • Standard level offset

Frage 112

Frage
The second type of dependence is?
Antworten
  • Name dependence
  • Data dependence
  • Control dependence

Frage 113

Frage
RAW (read after write)?
Antworten
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard corresponds to an output dependence
  • This hazard arises from an antidependence (or name dependence)

Frage 114

Frage
WAW (write after write)?
Antworten
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard arises from an antidependence (or name dependence)

Frage 115

Frage
WAR (write after read)?
Antworten
  • This hazard corresponds to an output dependence
  • This hazard is the most common type and corresponds to a true data dependence
  • This hazard arises from an antidependence (or name dependence)

Frage 116

Frage
What is the element “Read Operands” in simple five-stage pipeline?
Antworten
  • Decode instructions, check for structural hazards
  • Wait until no data hazards, then read operands

Frage 117

Frage
What is the ROB?
Antworten
  • Reorder buffer
  • Read only buffer
  • Relocate buffer

Frage 118

Frage
How many steps in instruction execution?
Antworten
  • 6
  • 5
  • 3
  • 4

Frage 119

Frage
How many restrictions RAW hazards through memory are maintained?
Antworten
  • 2
  • 3
  • 4

Frage 120

Frage
How many major flavors in Multiple-issue processors?
Antworten
  • 3
  • 4
  • 5

Frage 121

Frage
How many functions at Integrated Instruction Fetch Units
Antworten
  • 3
  • 4
  • 5

Frage 122

Frage
Speculation and the Challenge of Energy Efficiency consume excess energy in how many ways?
Antworten
  • 2
  • 3
  • 4

Frage 123

Frage
The hardware model represents the assumptions made for an ideal or perfect processor is as how many follow elements?
Antworten
  • 5
  • 4
  • 6

Frage 124

Frage
Infinite register renaming at The Hardware Model?
Antworten
  • There are an infinite number of virtual registers available
  • Branch prediction is perfect, all conditional branches are predicted exactly

Frage 125

Frage
Perfect Branch Prediction at the Hardware Model?
Antworten
  • There are an infinite number of virtual registers available
  • Branch prediction is perfect, all conditional branches are predicted exactly

Frage 126

Frage
Perfect caches at The Hardware Model?
Antworten
  • All memory accesses take one clock cycle
  • All memory addresses are known exactly
  • All conditional branches are predicted exactly

Frage 127

Frage
Perfect memory address alias analysis at The Hardware Model?
Antworten
  • All memory addresses are known exactly
  • All memory accesses take one clock cycle
  • All conditional branches are predicted exactly

Frage 128

Frage
Perfect jump prediction at The Hardware Model?
Antworten
  • All jumps are perfectly predicted
  • All conditional branches are predicted exactly
  • All memory addresses are known exactly

Frage 129

Frage
What is Personal mobile device (PMD)?
Antworten
  • A collection of wireless devices with multimedia user interfaces
  • A collection of computers with wireless network adapters
  • A collection of Clusters/Warehouse-scale computers

Frage 130

Frage
Where the embedded microprocessors are used?
Antworten
  • In microwaves, washing machines
  • In Personal Computers
  • In mobile phones

Frage 131

Frage
What functions has Instruction Set Architecture (ISA)?
Antworten
  • Serves as the boundary between the software and hardware?
  • Serves as the bridge between CPU and Memory
  • o Serves as the bridge between CPU and Cache

Frage 132

Frage
What is the TLP?
Antworten
  • Time Level Parallelism
  • Technology Level Parallelism
  • Task Level Parallelism

Frage 133

Frage
By Moore's law, growth rate in transistor count on a chip is doubling?
Antworten
  • every 8 to 12 months
  • every 12 to 16 months
  • every 18 to 24 months

Frage 134

Frage
How should a system architect or a user think about performance, power, and energy? From the viewpoint of a system designer, how many concerns are there?
Antworten
  • 3
  • 2
  • 4

Frage 135

Frage
What is the “Module reliability” in Dependability?
Antworten
  • A measure of the continuous service accomplishment from a reference initial instant
  • a measure of the service accomplishment with respect to the alternation between the two states of accomplishment and interruption.
  • a measure of the interruption

Frage 136

Frage
What is response time?
Antworten
  • the time between the start and the completion of an event
  • The time to get an information
  • The time spent on execution of a program

Frage 137

Frage
The guiding principle of reporting performance measurements should be?
Antworten
  • reproducibility
  • responsibility
  • creativity

Frage 138

Frage
What is Temporal Locality?
Antworten
  • recently accessed items are likely to be accessed in the near future
  • items whose addresses are near one another tend to be referenced close together in time
  • the nearest data stored in secondary memory

Frage 139

Frage
What is Spatial Locality?
Antworten
  • items whose addresses are near one another tend to be referenced close together in time
  • recently accessed items are likely to be accessed in the near future
  • the nearest data stored in secondary memory

Frage 140

Frage
What is Amdahl's law?
Antworten
  • Defines the speedup that can be gained by using a particular feature
  • Defines time spent on execution of a program
  • Defines data gained in one operation

Frage 141

Frage
The most popular scheme is set associative, where a set is?
Antworten
  • a group of blocks
  • a group of instructions
  • a group of comparatives

Frage 142

Frage
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Compulsory?
Antworten
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the cache cannot contain all the blocks needed during execution of a program
  • If the block placement strategy is not fully associative

Frage 143

Frage
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Capacity?
Antworten
  • If the cache cannot contain all the blocks needed during execution of a program
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the block placement strategy is not fully associative

Frage 144

Frage
The three Cs model sorts all misses into three simple categories: Compulsory, Capacity, Conflict. What is Conflict?
Antworten
  • If the block placement strategy is not fully associative
  • The very first access to a block cannot be in the cache, so the block must be brought into the cache
  • If the cache cannot contain all the blocks needed during execution of a program

Frage 145

Frage
The “natural” unit of organization of memory:
Antworten
  • Word
  • Document
  • Several Computer

Frage 146

Frage
Main element of cache memory is …
Antworten
  • Line
  • Word
  • String

Frage 147

Frage
Typical levels of Cache memories …
Antworten
  • 1,2,3 levels
  • 1,2,3,4,5 levels
  • Cache memories have no levels

Frage 148

Frage
Select internal memory …
Antworten
  • Hard Disk
  • CD-ROM
  • Processor registers

Frage 149

Frage
Select internal memory
Antworten
  • Hard Disk
  • Optical disk
  • Main memory

Frage 150

Frage
Select internal memory
Antworten
  • Cache
  • Magnetic tape
  • Optical disks

Frage 151

Frage
Select external memory:
Antworten
  • Processor registers
  • Cache
  • Main memory
  • Hard disks

Frage 152

Frage
Select external memory
Antworten
  • Optical Disk
  • Cache level 1
  • Registers of processor

Frage 153

Frage
Select external memory
Antworten
  • Magnetic tape
  • Main memory
  • All cache memories

Frage 154

Frage
Physical types of memories:
Antworten
  • Direct, Random
  • Direct, Access time
  • Semiconductor, Optical

Frage 155

Frage
Physical types of memories:
Antworten
  • Semiconductor, Magnetic
  • Word, Block
  • Direct, Random

Frage 156

Frage
Physical types of memories:
Antworten
  • Magneto-optical
  • Number of words
  • Number of bytes

Frage 157

Frage
Select correct memory hierarchy:
Antworten
  • Cache – Main Memory – Secondary storages
  • Secondary storages - Cache – Main Memory
  • Main Memory – Cache - Secondary storages

Frage 158

Frage
Select correct memory hierarchy:
Antworten
  • Processor registers – Cache memory – Main memory
  • Cache memory – Main memory - Processor registers
  • Cache memory – Processor registers - Main memory

Frage 159

Frage
External, nonvolatile memory is also referred to as …
Antworten
  • Auxiliary memory
  • Main memory
  • Levels of cache

Frage 160

Frage
Types of cache addresses:
Antworten
  • Logical, Physical
  • Direct, Associative
  • Set Associative

Frage 161

Frage
A logical cache stores data using …
Antworten
  • virtual addresses
  • virtual addresses and physical addresses
  • Physical addresses

Frage 162

Frage
The two basic forms of semiconductor random access memory are:
Antworten
  • dynamic RAM (DRAM) and static RAM (SRAM)
  • magnetic and optical
  • Winchester and optical disks

Frage 163

Frage
Main element of cache memory?
Antworten
  • Tag
  • Word
  • String

Frage 164

Frage
A number of chips can be grouped together to form …
Antworten
  • a memory bank
  • a memory tags
  • a memory lines

Frage 165

Frage
Data are recorded on and later retrieved from the disk via a conducting coil named:
Antworten
  • The arm
  • The slide
  • The head

Frage 166

Frage
The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as …
Antworten
  • multiple zoned recording
  • intersector gap
  • the constant angular velocity

Frage 167

Frage
To increase density, modern hard disk systems use a technique known as:
Antworten
  • multiple zone recording
  • the constant angular velocity

Frage 168

Frage
… can be removed and replaced with another disk.
Antworten
  • Processor registers
  • A non-removable disk
  • A removable disk

Frage 169

Frage
For most disks, the magnetizable coating is applied to both sides of the platter, which is then referred to as ...
Antworten
  • double sided
  • single sided
  • no sides

Frage 170

Frage
The set of all the tracks in the same relative position on the platter is referred to as …
Antworten
  • a cylinder
  • a square
  • a circle

Frage 171

Frage
On a movable head system, the time it takes to position the head at the track is known as …
Antworten
  • transfer time
  • access time
  • seek time

Frage 172

Frage
The operating system …
Antworten
  • is the software that controls the execution of programs on a processor and that manages the processor’s resources.
  • is one which is understandable by us humans
  • is a collection of Clusters/Warehouse-scale computers
  • a program that directly executes instructions written in a programming language

Frage 173

Frage
The most important functions of the Operating System are:
Antworten
  • The scheduling of processes, or tasks
  • Compile C++ program codes
  • Interpret PHP program codes
  • Provide drivers for the remote devices

Frage 174

Frage
The important function of the Operating System is
Antworten
  • Memory management
  • Provide compiler for high level programming languages
  • Increase size of cache

Frage 175

Frage
How is the following service called? The Operating System provides a variety of facilities and services, such as editors and debuggers, to assist the programmer in creating programs…
Antworten
  • Program execution
  • Access to I/O devices
  • Program creation

Frage 176

Frage
How is the following service called? A number of tasks need to be performed to execute a program. Instructions and data must be loaded into main memory, I/O devices and files must be initialized, and other resources must be prepared. The Operating System handles all of this for the user.
Antworten
  • Program creation
  • Access to I/O devices
  • Program execution

Frage 177

Frage
How is the following service called? Each I/O device requires its own specific set of instructions or control signals for operation. The Operating System takes care of the details so that the programmer can think in terms of simple reads and writes.
Antworten
  • Access to I/O devices
  • Program execution
  • Program creation

Frage 178

Frage
How is the following service called? In the case of a shared or public system, the Operating System controls access to the system as a whole and to specific system resources.
Antworten
  • Controlled access to files
  • Access to I/O devices
  • System access

Frage 179

Frage
How is the following service called? These are internal and external hardware errors, such as a memory error, or a device failure or malfunction; and various software errors, such as arithmetic overflow, attempt to access forbidden memory location, and inability of the OS to grant the request of an application. In each case, the Operating System must make the response that clears the error condition with the least impact on running applications.
Antworten
  • Error detection and response
  • System access
  • Controlled access to files

Frage 180

Frage
How is the following service called? A good Operating System collects usage statistics for various resources and monitor performance parameters such as response time. On any system, this information is useful in anticipating the need for future enhancements and in tuning the system to improve performance.
Antworten
  • Accounting
  • System access
  • Controlled access to files

Frage 181

Frage
Select two independent dimensions of the Operating System:
Antworten
  • batch and interactive
  • batch and computer operator
  • Interactive and computer operator

Frage 182

Frage
Select the ARM Memory-Management Parameter according to this description. These bits control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, a Permission Fault is raised.
Antworten
  • Access Permission (AP), Access Permission Extension (APX)
  • Bufferable (B) bit
  • Cacheable (C) bit

Frage 183

Frage
Select ARM Memory-Management Parameter according to this description. Determines, with the TEX bits, how the write buffer is used for cacheable memory.
Antworten
  • Bufferable (B) bit
  • Cacheable (C) bit
  • Type Extension (TEX)

Frage 184

Frage
Different types of parallelism in applications like:
Antworten
  • Data-level Parallelism
  • Task-level Parallelism
  • Instruction-level Parallelism
  • All of the above
Zusammenfassung anzeigen Zusammenfassung ausblenden

Möchten Sie mit GoConqr kostenlos Ihre eigenen Quiz erstellen? eigenen Mehr erfahren.

ähnlicher Inhalt

Französisch für Anfänger
JohannesK
PuKW Step 6 Teil 1
Mona Les
Öff. Recht - Streitigkeiten Staatshaftungsrecht
myJurazone
Aufstieg der NSDAP
Anina Hagi
Unsere Erde - Sonnensystem, Klima, Erdschichten etc.
rezension1
Deutsch Partizip Perfekt - unregelmäßige Verben
Claus Lenz
Purchase -to -Pay Geschäftsprozess
zok42.com
Marketing-Mix
Marion Engel
EC Klinische Psychologie
Sandra S.
AVO 2017
Schmolli Schmoll
Vetie: Geflügelkrankheiten 2020 (Matrikel 2015)
Ro F
Bibliothek durchsuchen