Frage 1
Antworten
-
is amount of data that can be in flight at the same time (Little’s Law)
-
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses
per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
Frage 2
Frage
What occurs at Intruction fetches when we speak about Common And Predictable Memory
Reference Patterns?
Antworten
-
n loop iterations
-
subroutine call
-
vector access
Frage 3
Frage
What occurs at Stack access when we speak about Common And Predictable Memory
Reference Patterns?
Antworten
-
n loop iterations
-
subroutine call
-
vector access
Frage 4
Frage
What occurs at Data access when we speak about Common And Predictable Memory
Reference Patterns?
Antworten
-
subroutine call
-
n loop iterations
-
vector access
Frage 5
Antworten
-
No Write Allocate, Write Allocate
-
Write Through, Write Back
Frage 6
Antworten
-
No Write Allocate, Write Allocate
-
Write Through, Write Back
Frage 7
Frage
Average Memory Access Time is equal:
Antworten
-
Hit Time * ( Miss Rate + Miss Penalty )
-
Hit Time - ( Miss Rate + Miss Penalty )
-
Hit Time / ( Miss Rate - Miss Penalty )
-
Hit Time + ( Miss Rate * Miss Penalty )
Frage 8
Antworten
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines)
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
Frage 9
Antworten
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines)
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
first-reference to a block, occur even with infinite cache
Frage 10
Antworten
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity (loop over 3 cache lines)
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy (loop over 5 cache
lines)
Frage 11
Frage
Algorithm for Cache HIT:
Antworten
-
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from
cache
-
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> return
copy of data from cache
Frage 12
Frage
Algorithm for Cache MISS:
Antworten
-
Processor issues load request to cache -> Compare request address to cache tags and see if there is a match -> Read
block of data from main memory -> Replace victim block in cache with new block -> return copy of data from cache
-
Processor issues load request to cache -> Read block of data from main memory -> return copy of data from cache
-
Processor issues load request to cache -> Replace victim block in cache with new block -> return copy of data from
cache
Frage 13
Frage
The formula of “Iron Law” of Processor Performance:
Antworten
-
time/program = instruction/program * cycles/instruction * time/cycle
-
time/program = instruction/program * cycles/instruction + time/cycle
-
time/program = instruction/program + cycles/instruction * time/cycle
Frage 14
Antworten
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 15
Antworten
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
An instruction depends on a data value produced by an earlier instruction
Frage 16
Antworten
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Frage 17
Frage
What is a Bandwidth:
Antworten
-
a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI
= 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Frage 18
Frage
What is a Bandwidth-Delay Product:
Antworten
-
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI
= 1 requires at least 1 + m memory accesses per cycle
-
is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Frage 19
Frage
What is Computer Architecture?
Antworten
-
the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use
them
-
is the design of the abstraction/implementation layers that allow us to execute information processing applications
efficiently using manufacturing technologies
-
is a group of computer systems and other computing hardware devices that are linked together through communication
channels to facilitate communication and resource-sharing among a wide range of users
Frage 20
Frage
Least Recently Used (LRU):
Antworten
-
FIFO with exception for most recently used block(s)
-
Used in highly associative caches
-
cache state must be updated on every access
Frage 21
Antworten
-
Write Through – write both cache and memory, generally higher traffic but simpler to design
-
write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
-
No Write Allocate – only write to main memory
Frage 22
Frage
Reduce Miss Rate: Large Cache Size. Empirical Rule of Thumb:
Antworten
-
None of them
-
If cache size is doubled, miss rate usually drops by about √2
-
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
Frage 23
Frage
Reduce Miss Rate: High Associativity. Empirical Rule of Thumb:
Antworten
-
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
-
None of them
-
If cache size is doubled, miss rate usually drops by about √2
Frage 24
Frage
Exploit temporal locality:
Frage 25
Frage
Exploit spatial locality:
Frage 26
Antworten
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Frage 27
Antworten
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
-
Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
-
An instruction depends on a data value produced by an earlier instruction
Frage 28
Frage
What is the access time?
Antworten
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
None of them
Frage 29
Frage
What is the cycle time?
Antworten
-
The minimum time between requests to memory
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of them
Frage 30
Frage
What does SRAM stands for?
Antworten
-
System Random Access memory
-
Static Random Access memory
-
Short Random Accessmemory
-
None of them
Frage 31
Frage
What does DRAM stands for?
Antworten
-
Dataram Random Access memory
-
Dual Random Access memory
-
Dynamic Random Access memory
Frage 32
Frage
What does DDR stands for?
Antworten
-
None of them
-
Double data reaction
-
Dual data rate
-
Double data rate
Frage 33
Frage
What is kernel process?
Antworten
-
Provide at least two modes, indicating whether the running process is a user process or an
operating system process
-
Provide a portion of the processor state that a user process can use but not write
-
Provide at least five modes, indicating whether the running process is a user process or an
operating system process
-
None of them
Frage 34
Frage
Which one is NOT concerning to pitfall?
Antworten
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
-
Predicting cache performance of one program from another
-
Over emphasizing memory bandwidth in DRAMs
Frage 35
Frage
Which one is concerning to fallacy?
Antworten
-
Over emphasizing memory bandwidth in DRAMs
-
Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to
be virtualizable
-
Predicting cache performance of one program from another
-
Simulating enough instructions to get accurate performance measures of the memory hierarchy
Frage 36
Frage
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “System response time” - ?:
Antworten
-
The time from the reception of the response until the user begins to enter the next command
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
Frage 37
Frage
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Think time” - ?:
Antworten
-
The time from the reception of the response until the user begins to enter the next command
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
Frage 38
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time
server” - :
Antworten
-
Average time per task in the queue
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally represented
by the symbol μ in many queuing texts
Frage 39
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time
queue” - :
Antworten
-
Average time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts
-
Average time per task in the queue
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 40
Frage
Little’s Law and a series of definitions lead to several useful equations for “Time
system” - :
Antworten
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts
-
Average time per task in the queue
Frage 41
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :
Frage 42
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:
Frage 43
Frage
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Frage 44
Frage
How many issue queue used in Distributed Superscalar 2 and Exceptions:
Frage 45
Frage
How many instructions used in Distributed Superscalar 2 and Exceptions?
Frage 46
Frage
How many issue queue used in Centralized Superscalar 2 and Exceptions?
Frage 47
Frage
Which of the following formula is true about Issue Queue for “Instruction Ready”:
Antworten
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc0)&& no structural hazards
-
Instruction Ready = (!Vsrc0 || !Psrc1)&&(!Vsrc1 || !Psrc0)&& no structural hazards
-
Instruction Ready = (!Vsrc0 || !Psrc0)&&(!Vsrc1 || !Psrc1)&& no structural hazards
-
Instruction Ready = (!Vsrc1 || !Psrc1)&&(!Vsrc0 || !Psrc1)&& no structural hazards
Frage 48
Frage 49
Antworten
-
Read Only Buffer
-
Reorder Buffer
-
Reload Buffer
-
Recall Buffer
Frage 50
Antworten
-
Finished Star Buffer
-
Finished Stall Buffer
-
Finished Store Buffer
-
Finished Stack Buffer
Frage 51
Antworten
-
Pure Register File
-
Physical Register File
-
Pending Register File
-
Pipeline Register File
Frage 52
Antworten
-
Scalebit
-
Scaleboard
-
Scorebased
-
Scoreboard
Frage 53
Frage
How many stages used in Superscalar (Pipeline)?
Frage 54
Frage
What is about Superscalar means “F-D-X-M-W”?
Antworten
-
Fetch, Decode, Instruct, Map, Write
-
Fetch, Decode, Execute, Memory, Writeback
-
Fetch, Decode, Excite, Memory, Write
-
Fetch, Decode, Except, Map, Writeback
Frage 55
Frage
Speculating on Exceptions “Prediction mechanism” is -
Antworten
-
None of them
-
Only write architectural state at commit point, so can throw away partially executed instructions after
exception
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
Frage 56
Frage
Speculating on Exceptions “Check prediction mechanism” is -
Antworten
-
The way in which an object is accessed by a subject
-
Exceptions detected at end of instruction execution pipeline, special hardware for various exception types
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
None of them
Frage 57
Frage
Speculating on Exceptions “Recovery mechanism” is
Antworten
-
None of them
-
An entity capable of accessing objects
-
Exceptions are rare, so simply predicting no exceptions is very accurate
-
Only write architectural state at commit point, so can throw away partially executed instructions after
exception
Frage 58
Antworten
-
Rename Table
-
Recall Table
-
Relocate Table
-
Remove Table
Frage 59
Antworten
-
Free Launch
-
Free List
-
Free Leg
-
Free Last
Frage 60
Antworten
-
Internal Queue
-
Instruction Queue
-
Issue Queue
-
Interrupt Queue
Frage 61
Frage
At VLIW “Superscalar Control Logic Scaling” which parameters are used?
Antworten
-
Width and Height
-
Width and Lifetime
-
Time and Cycle
-
Length and Addition
Frage 62
Frage
Out-of-Order Control Complexity MIPS R10000 which element is in Control
Logic?
Antworten
-
Register name
-
Instruction cache
-
Data tags
-
Data cache
Frage 63
Frage
Out-of-Order Control Complexity MIPS R10000 which element is not in Control
Logic?
Antworten
-
Integer Datapath
-
CLK
-
Address Queue
-
Free List
Frage 64
Frage 65
Frage
At VLIW by “performance and loop iteration” which time is longer?
Antworten
-
Loop Unrolled
-
Software Pipelined
Frage 66
Frage
At VLIW by “performance and loop iteration” which time is shorter?
Antworten
-
Loop Unrolled
-
Software Pipelined
Frage 67
Frage
At VLIW Speculative Execution, which of this solution is true about problem:
Branches restrict compiler code motion?
Frage 68
Frage
At VLIW Speculative Execution, which of this solution is true about problem:
Possible memory hazards limit code scheduling:
Frage 69
Antworten
-
Advanced Load Address Table
-
Allocated Link Address Table
-
Allowing List Address Table
-
Addition Long Accessibility Table
Frage 70
Frage
At VLIW Multi-Way Branches, which of this solution is true about problem: Long
instructions provide few opportunities for branches:
Frage 71
Frage
What is a Compulsory?
Antworten
-
first-reference to a block, occur even with infinite cache
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
misses that occur because of collisions due to less than full associativity
Frage 72
Frage
What is a Capacity?
Antworten
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
misses that occur because of collisions due to less than full associativity
-
first-reference to a block, occur even with infinite cache
Frage 73
Frage
What is a Conflict?
Antworten
-
misses that occur because of collisions due to less than full associativity
-
first-reference to a block, occur even with infinite cache
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
Frage 74
Frage
In Multilevel Caches “Local miss rate” equals =
Antworten
-
misses in cache / accesses to cache
-
misses in cache / CPU memory accesses
-
misses in cache / number of instructions
Frage 75
Frage
In Multilevel Caches “Global miss rate” equals =
Antworten
-
misses in cache / CPU memory accesses
-
misses in cache / accesses to cache
-
misses in cache / number of instructions
Frage 76
Frage
In Multilevel Caches “Misses per instruction” equals =
Antworten
-
misses in cache / number of instructions
-
misses in cache / accesses to cache
-
misses in cache / CPU memory accesses
Frage 77
Frage
Non-Blocking Cache Timeline for “Blocking Cache” the sequence is - ?
Antworten
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Frage 78
Frage
Non-Blocking Cache Timeline for “Hit Under Miss” the sequence is -?
Antworten
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->CPU time
Frage 79
Frage
Non-Blocking Cache Timeline for “Miss Under Miss” the sequence is -?
Antworten
-
CPU time->Cache Miss->Miss->Stall on use->Miss Penalty->Miss Penalty->CPU time
-
CPU time-Cache Miss-Miss Penalty-CPU time
-
CPU time->Cache Miss->Hit->Stall on use->Miss Penalty->CPU time
Frage 80
Frage
What does mean MSHR?
Antworten
-
Miss Status Handling Register
-
Map Status Handling Reload
-
Mips Status Hardware Register
-
Memory Status Handling Register
Frage 81
Antworten
-
Miss Address File
-
Map Address File
-
Memory Address File
Frage 82
Frage
At Critical Word First for Miss Penalty chose correct sequence of Basic Blocking
Cache “Order of fill”:
Antworten
-
0,1,2,3,4,5,6,7
-
3,4,5,6,7,0,1,2
Frage 83
Frage
At Critical Word First for Miss Penalty chose correct sequence of Blocking
Cache with Critical Word first “Order of fill”:
Antworten
-
3,4,5,6,7,0,1,2
-
0,1,2,3,4,5,6,7
Frage 84
Frage
Storage Systems, “Larger block size to reduce miss rate”
Antworten
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase
the block size
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
Frage 85
Frage
Storage Systems, “Bigger caches to reduce miss rate” -
Antworten
-
The obvious way to reduce capacity misses is to increase cache capacity
-
Obviously, increasing associativity reduces conflict misses
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase
the block size
Frage 86
Frage
Storage Systems, “Higher associativity to reduce miss rate” -
Antworten
-
Obviously, increasing associativity reduces conflict misses
-
The obvious way to reduce capacity misses is to increase cache capacity
-
The simplest way to reduce the miss rate is to take advantage of spatial locality and increase
the block size
Frage 87
Frage
In Non-Blocking Caches what does mean “Critical Word First”?
Antworten
-
Request the missed word first from memory and send it to the processor as soon as it arrives;
let the processor continue execution while filling the rest of the words in the block
-
Fetch the words in normal order, but as soon as the requested word of the block arrives,
send it to the processor and let the processor continue execution
Frage 88
Frage
In Non-Blocking Caches what does mean “Early restart”?
Antworten
-
Fetch the words in normal order, but as soon as the requested word of the block arrives, send
it to the processor and let the processor continue execution
-
Request the missed word first from memory and send it to the processor as soon as it
arrives; let the processor continue execution while filling the rest of the words in the block
Frage 89
Frage
A virus classification by target includes the following categories, What is a File
infector?
Antworten
-
A typical approach is as follows
-
Infects files that the operating system or shell consider to be executable
-
The key is stored with the virus
-
Far more sophisticated techniques are possible
Frage 90
Antworten
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,” although
the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
-
This organization was inspired by applying memory-style error correcting codes to disks
Frage 91
Antworten
-
Also called mirroring or shadowing, there are two copies of every piece of data
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,”
although the data may be striped across the disks in the array
-
This organization was inspired by applying memory-style error correcting codes to disks
Frage 92
Antworten
-
This organization was inspired by applying memory-style error correcting codes to disks
-
It has no redundancy and is sometimes nicknamed JBOD, for “just a bunch of disks,”
although the data may be striped across the disks in the array
-
Also called mirroring or shadowing, there are two copies of every piece of data
Frage 93
Antworten
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk failed
-
Many applications are dominated by small accesses
-
Also called mirroring or shadowing, there are two copies of every piece of data
Frage 94
Antworten
-
Many applications are dominated by small accesses
-
Since the higher-level disk interfaces understand the health of a disk, it’s easy to figure out which disk
failed
-
Also called mirroring or shadowing, there are two copies of every piece of data
Frage 95
Frage
At storage systems Gray and Siewiorek classify faults what does mean
“Hardware faults”? :
Antworten
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
-
Mistakes by operations and maintenance personnel
Frage 96
Frage
At storage systems Gray and Siewiorek classify faults what does mean “Design
faults”? :
Antworten
-
Faults in software (usually) and hardware design (occasionally)
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Mistakes by operations and maintenance personnel
Frage 97
Frage
At storage systems Gray and Siewiorek classify faults what does mean
“Operation faults”? :
Antworten
-
Mistakes by operations and maintenance personnel
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
-
Faults in software (usually) and hardware design (occasionally)
Frage 98
Frage
At storage systems Gray and Siewiorek classify faults what does mean
“Environmental faults”? :
Antworten
-
Fire, flood, earthquake, power failure, and sabotage
-
Faults in software (usually) and hardware design (occasionally)
-
Devices that fail, such as perhaps due to an alpha particle hitting a memory cell
Frage 99
Frage
If we talk about storage systems an interaction or transaction with a computer is
divided for first what is an “Entry time” - ? :
Antworten
-
The time for the user to enter the command
-
The time between when the user enters the command and the complete response is displayed
-
The time from the reception of the response until the user begins to enter the next command
Frage 100
Frage
If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “System response time” - ?:
Antworten
-
The time between when the user enters the command and the complete response is displayed
-
The time for the user to enter the command
-
The time from the reception of the response until the user begins to enter the next command
Frage 101
Frage
If we talk about storage systems an interaction or transaction with a
computer is divided for first what is an “Think time” - ?:
Antworten
-
The time from the reception of the response until the user begins to enter the next command
-
The time for the user to enter the command
-
The time between when the user enters the command and the complete response is displayed
Frage 102
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Time server” - :
Antworten
-
Average time to service a task; average service rate is 1/Time server traditionally represented
by the symbol μ in many queuing texts
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time per task in the queue
Frage 103
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Time queue” - :
Antworten
-
Average time per task in the queue
-
Average time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Frage 104
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Time system” - :
Antworten
-
Average time/task in the system, or the response time, which is the sum of Time queue and Time server
-
Average time to service a task; average service rate is 1/Time server traditionally
represented by the symbol μ in many queuing texts
-
Average time per task in the queue
Frage 105
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Length server” - :
Frage 106
Frage
Little’s Law and a series of definitions lead to several useful equations for
“Length queue” -:
Frage 107
Frage
How many size of Cache L1 is true approximately? :
Frage 108
Frage
How many size of Cache L2 is true approximately?
Frage 109
Frage
How many size of Cache L3 is true approximately?
Frage 110
Frage
How many main levels of Cache Memory?
Frage 111
Frage
What is a “Synchronization” in Cache Memory?
Frage 112
Frage
What is a “Kernel” in Cache Memory?
Frage 113
Frage
What is a “Synchronization” in Cache Memory?
Frage 114
Frage
Network performance depends of what?
Frage 115
Frage
The time between the start and the completion of an event ,such as milliseconds
for a disk access is...
Antworten
-
latency
-
bandwidth
-
throughput
-
performance
Frage 116
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Total amount of work done in a given time ,such as megabytes per second for disk
transfer...
Antworten
-
bandwidth
-
latency
-
throughput
-
performance
Frage 117
Frage
Learning curve itself is best measured by change in...
Frage 118
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Products that are sold by multiple vendors in large volumes and are essentialy
identical
Antworten
-
commodities
-
boxes
-
folders
-
files
Frage 119
Frage
Integrated circuit processes are charecterized by the
Antworten
-
feature size
-
permanent size n
-
compex size
-
fixed size
Frage 120
Frage
For CMOS chips, the traditional dominant energy consumption has been in
switching transistors, called ____
Antworten
-
dynamic power
-
physical energy
-
constant supply
-
simple battery
Frage 121
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Manufacturing costs that decrease over time are ____
Antworten
-
the learning curve
-
the cycled line
-
the regular option
-
the final loop
Frage 122
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Volume is a ________ key factor in determining cost
Frage 123
Frage
The most companies spend only ____________ of their income on R&D, which
includes all engineering.
Antworten
-
4% to 12%
-
15% to 30%
-
1% to 17%
-
30% to 48%
Frage 124
Frage
Systems alternate between two states of service with respect to an SLA:
Antworten
-
1. Service accomplishment, where the service is delivered as specified
2. Service interruption, where the delivered service is different from the SLA
-
1. Service accomplishment, where the service is not delivered as specified
2. Service interruption, where the delivered service is different from the SLA
-
1. Service accomplishment, where the service is not delivered as specified
2. Service interruption, where the delivered service is not different from the SLA
-
1. Service accomplishment, where the service is delivered as specified
2. Service interruption, where the delivered service is not different from the SLA
Frage 125
Frage
Desktop benchmarks divide into __ broad classes:
Frage 126
Antworten
-
mean time to failure
-
mean time to feauture
-
mean this to failure
-
my transfers to failure
Frage 127
Frage
A widely held rule of thumb is that a program spends __ of its execution time in
only __ of the code.
Antworten
-
90% 10%
-
50% 50%
-
70% 30%
-
89% 11%
Frage 128
Frage
(Performance for entire task using the enhancement when possible) / (Performance
for entire task without using the enhancement) is equals to:
Antworten
-
Speedup
-
Efficiency
-
Probability
-
Ration
Frage 129
Frage
Which of the following descriptions corresponds to static power?
Antworten
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Proportional to the product of the number of switching transistors and the switching rate
Probability
-
Proportional to the product of the number of switching transistors and the switching rate
-
All of the above
Frage 130
Frage
Which of the following descriptions corresponds to dynamic power?
Antworten
-
Proportional to the product of the number of switching transistors and the switching rate
-
Grows proportionally to the transistor count (whether or not the transistors are switching)
-
Certainly a design concern
-
None of the above
Frage 131
Frage
Which of the written below is NOT increase power consumption?
Antworten
-
Increasing multithreading
-
Increasing performance
-
Increasing multiple cores
-
Increasing multithreading (V baze tak napisano)
Frage 132
Frage
Growing performance gap between peak and sustained performance translates to
increasing energy per unit of performance, when:
Antworten
-
The number of transistors switching will be proportional to the peak issue rate, and the
performance is proportional to the sustained rate
-
The number of transistors switching will be proportionalto the sustained rate, and the
performance is proportionalto the peak issue rate
-
The number of transistors switching will be proportional to the sustained rate
-
The performance is proportional to the peak issue rate
Frage 133
Frage
If we want to sustain four instructions per clock
Antworten
-
We must fetch more, issue more, and initiate execution on more than four instructions
-
We must fetch less, issue more, and initiate execution on more than two instructions
-
We must fetch more, issue less, and initiate execution on more than three instructions
-
We must fetch more, issue more, and initiate execution on less than five instructions
Frage 134
Frage
If speculation were perfect, it could save power, since it would reduce the execution time and
save _____________, while adding some additional overhead to implement
Antworten
-
Static power
-
Dynamic power
-
Processing rate
-
Processor state
Frage 135
Frage
When speculation is not perfect, it rapidly becomes energy inefficient, since it requires
additional ___________ both for the incorrect speculation and for the resetting of the processor
state
Antworten
-
Dynamic power
-
Static power
-
Processing rate
-
Processor state
Frage 136
Frage
Which of these concepts is NOT illustrated case study by Wen-mei W. Hwu and John W.
Sias
Antworten
-
Achievable ILP with software resource constraints
-
Limited ILP due to software dependences
-
Achievable ILP with hardware resource constraints
-
Variability of ILP due to software and hardware interaction
Frage 137
Frage
What is a hash table?
Antworten
-
Popular data structure for organizing a large collection of data items so that one can quickly
answer questions
-
Popular data structure for updating large collections, so that one can hardly answer questions
-
Popular tables for organizing a large collection of data structure
-
Popular data structure for deletingsmall collections of data items so that one can hardly
answer questions
Frage 138
Frage
Which of these is NOT characteristics of recent highperformance microprocessors?
Frage 139
Frage
How this process called: “Operations execute as soon as their operands are available”
Frage 140
Frage
For what the reorder buffer is used :
Antworten
-
To pass results among instructions that may be speculated
-
To pass parameters through instructions that may be speculated
-
To get additional registers in the same way as the reservation stations
-
To control registers
Frage 141
Frage
How many fields contains the entry in the ROB:
Frage 142
Frage
Choose correct fields of entry in the ROB:
Antworten
-
the instruction type, the destination field, the value field, and the ready field
-
the source type, the destination field, the value field, and the ready field
-
the program type, the ready field, the parameter field, the destination field
-
the instruction type, the destination field, and the ready field
Frage 143
Frage
Choose the steps of instruction execution:
Antworten
-
issue, execute, write result, commit
-
execution, commit, rollback
-
issue, execute, override, exit
-
begin, write, interrupt, commit
Frage 144
Frage
Which one is not the major flavor of Multiple-issue processors
Antworten
-
statistically superscalar processors
-
dynamically scheduled superscalar processors
-
statically scheduled superscalar processors
-
VLIW (very long instruction word) processors
Frage 145
Frage
Which Multiple-issue processors has not the hardware hazard detection
Antworten
-
EPIC
-
Superscalar(dynamic)
-
Superscalar(static)
-
Superscalar(speculative)
Frage 146
Frage 147
Frage
Examples of superscalar(static):
Frage 148
Frage
Examples of superscalar(dynamic) :
Frage 149
Frage
Examples of VLIW/LIW:
Frage 150
Frage
A branch-prediction cache that stores the predicted address for the next instruction after a
branch
Antworten
-
branch-target buffer
-
data buffer
-
frame buffer
-
optical buffer
Frage 151
Frage
Buffering the actual target instructions allows us to perform an optimization which called:
Antworten
-
branch folding
-
Branch prediction
-
Target instructions
-
Target address
Frage 152
Frage
Which is not the function of integrated instruction fetch unit:
Antworten
-
Instruction memory commit
-
Integrated branch prediction
-
Instruction prefetch
-
Instruction memory access and buffering
Frage 153
Frage
What is the simple technique that predicts whether two stores or a load and a store refer to
the same memory address:
Antworten
-
Address aliasing prediction
-
Branch prediction
-
Integrated branch prediction
-
Dynamic branch prediction
Frage 154
Frage
How to decrypt RISC?
Antworten
-
Reduced Instruction Set Computer
-
Recall Instruction Sell Communication
-
Rename Instruction Sequence Corporation
-
Red Instruction Small Computer
Frage 155
Frage
The ideal pipeline CPI is a measure of …
Antworten
-
the maximum performance attainable by the implementation
-
the maximum performance attainable by the instruction
-
the minimum performance attainable by the implementation
-
the minimum performance attainable by the instruction
Frage 156
Frage
What is the Pipeline CP = ?
Antworten
-
deal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
-
deal pipeline CPU + Data hazard stalls + Control stalls
-
deal pipeline CPU + deal pipeline CPI + Data hazard stalls + Control stalls
-
Structural stalls + Data hazard stalls + Control stalls
Frage 157
Frage
The simplest and most common way to increase the ILP is …?
Antworten
-
to exploit parallelism among iterations of a loop
-
to exploit minimalism among iterations of a loop
-
to destroy iterations of a loop
-
to decrease the minimalism of risk
Frage 158
Frage
The simplest and most common way to increase the ILP is to exploit parallelism among
iterations of a loop. How is often called?
Frage 159
Frage
In parallelism have three different types of dependences, tagging him:
Antworten
-
data dependences , name dependences , and control dependences
-
data dependences , name dependences , and surname dependences
-
datagram dependences , name dependences , and animal dependences
-
no correct answers
Frage 160
Frage
What is Name dependence?
Antworten
-
name dependence occurs when two instructions use the same register or memory location
-
name dependence occurs when five or more instructions use the same register or memory location
-
name dependence occurs when instructions use the same name
-
All answers is correct
Frage 161
Frage
When occurs an output dependence?
Antworten
-
When i and instruction j write the same register or memory location
-
when i and instruction j write the same name
-
when i and instruction j write the same adress or memory location
-
All answers is correct
Frage 162
Frage
What is RAW (read after write)?
Antworten
-
when j tries to read a source before i writes it, so j incorrectly gets the old value
-
when i tries to read a source before j writes it, so j correctly gets the old value
-
when j tries to write a source before i writes it
-
when a tries to write a source before b read it, so a incorrectly gets the old value
Frage 163
Frage
What is given is not a hazard?
Frage 164
Frage
A simple scheme for increasing the number of instructions relative to the branch and
overhead instructions is…?
Antworten
-
loop unrolling
-
RAR
-
loop-level
-
loop rolling
Frage 165
Frage
Effect that results from instruction scheduling in large code segments is called…?
Antworten
-
register pressure
-
loop unrolling
-
loop-level
-
registration
Frage 166
Frage
The simplest dynamic branch-prediction scheme is a
Antworten
-
branch-prediction buffer
-
branch buffer
-
All answers correct
-
registration
Frage 167
Frage
Branch predictors that use the behavior of other branches to make a prediction are called
Frage 168
Frage
How many branch-selected entries are in a (2,2) predictor that has a total of 8K bits in the
prediction buffer? If we know that Number of prediction entries selected by the branch = 8K
Antworten
-
the number of prediction entries selected by the branch = 1K.
-
the number of prediction entries selected by the branch = 2K.
-
the number of prediction entries selected by the branch = 8K.
-
the number of prediction entries selected by the branch = 4K.
Frage 169
Frage
What is the compulsory in Cs model?
Antworten
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache.
Compulsory misses are those that occur even if you had an infinite cache
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later
retrieved
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Frage 170
Frage
What is capacityin Cs model?
Antworten
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The very first access to a block cannot be in the cache, so the block must be brought into the
cache. Compulsory misses are those that occur even if you had an infinite cache.
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Frage 171
Frage
What is conflict in Cs model?
Antworten
-
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory
and capacity misses) will occur because a block may be discarded and later retrieved if conflicting
blocks map to its set
-
The very first access to a block cannot be in the cache, so the block must be brought into the
cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses
(in addition to compulsory misses) will occur because of blocks being discarded and later
retrieved
-
None of them
Frage 172
Frage
Choose the benefit of Cache Optimization.
Antworten
-
Larger block size to reduce miss rate
-
Bigger caches to increase miss rat
-
Single level caches to reduce miss penalty
-
None of them
Frage 173
Frage
Choose the strategy of Seventh Optimization.
Frage 174
Frage
Choose the Eight Optimization
Antworten
-
Merging Write Buffer to Reduce Miss Penalty
-
Critical word first
-
Nonblocking Caches to Increase Cache Bandwidth
-
Trace Caches to Reduce Hit Time
Frage 175
Frage
Choose the Eleventh Optimization
Antworten
-
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
-
Merging Write Buffer to Reduce Miss Penalty
-
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
-
None of them
Frage 176
Frage
What is the access time?
Antworten
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
None of them
Frage 177
Frage
What is the cycle time?
Antworten
-
The minimum time between requests to memory
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of them
Frage 178
Frage
How much in percentage single-processor performance improvement has dropped to
less than?
Frage 179
Frage
How many elements of the Instruction Set Architecture (ISA):
Frage 180
Frage
What is the Thread Level Parallelism –
Antworten
-
Exploits either data-level parallelism or task-level parallelism in a tightly coupled hardware model that
allows for interaction among parallel threads.
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Frage 181
Frage
What is the PMD in computer classes?
Antworten
-
Personal mobile device
-
Powerful markup distance
-
Percentage map device
Frage 182
Frage
What is the Instruction Level Parallelism:
Antworten
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a
medium levels using ideas like speculative execution.
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel
Frage 183
Frage
How many elements in Trends of Technology?
Frage 184
Frage
What is the Vector Architecture and Graphic Processor Units (GPUs) –
Antworten
-
Exploit data-level parallelism by applying a single instruction to a collection of data in parallel.
-
Exploits data-level parallelism at modest levels with compiler help using ideas like pipelining and at a
medium levels using ideas like speculative execution
-
Exploits parallelism among largely decoupled tasks specified by the programmer or operating system.
Frage 185
Frage
How many Optimizations’ in Cache memory Performance?
Frage 186
Frage
What is the Reducing the Miss Rate?
Antworten
-
Time Optimization
-
Compiler Optimization
-
Performance Optimization
Frage 187
Frage
What is the Spatial Locality?
Frage 188
Frage
What is the Temporal Locality?
Frage 189
Frage
True formula of Module availability (MTTF – mean time to failure, MTTR – mean
time to repair)?
Antworten
-
MTTF / (MTTF + MTTR)
-
MTTF * (MTTF + MTTR)
-
MTTF * (MTTF - MTTR)