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1. What is not a main structural element of a computer system?
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● Operating system
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● System Bus
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● I/O Modules
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● Main Memory
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● Processor
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2. Which of the following registers are used by the processor to exchange data
with memory?
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● I/OAR and I/OBR
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● Program status word
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● PC and IR
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● MAR and MBR
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3. Which of the following registers are used by the processor to exchange data
with input/output module?
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● I/OAR and I/OBR
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● Program status word
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● PC and IR
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● MAR and MBR
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4. Which of the following element of a computer system controls the operation of
the computer and performs its data processing functions?
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● Processor
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● I/O modules
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● Main memory
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● System bus
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5. Which of the following element of a computer system stores data and
programs?
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● I/O modules
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● Processor
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● System bus
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● Main memory
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6. Which of the following provides for communication among elements of a
computer system?
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● I/O modules
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● Processor
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● System bus
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● Main memory
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7. Which of the following element of a computer system moves data between the
computer and its external environment?
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● I/O modules
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● System bus
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● Processor
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● Main memory
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8. The processor contains a single data register, called
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9. This register specifies a particular input/output device
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10. This register is used for the exchange of data between an I/O module and the
processor
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11. This register contains the data to be written into memory or which receives the
data read from memory
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12. This register specifies the location in memory for the next read or write
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13. Index register, segment register, and stack register are example of:
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● Address register
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● Memory register
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Memory buffer register
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Memory quality register
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14. Which register contains the address of the next instruction to be fetched?
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● process counter
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● program counter
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● execution register
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● instruction register
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15. Which register contains the instruction most recently fetched?
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● process counter
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● program counter
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● execution register
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● instruction register
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16. Which register contains condition codes set by the processor hardware as the
result of operations?
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● Stack pointer
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● Program status word
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● Accumulator
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● Program counter
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17. The figure 1.4.
1. What is the address of the instruction that is being executed?
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17.2. What is the address of the instruction that is being executed?
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17.3. What is the address of the instruction that is being executed?
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17.4. What is the address of the instruction that will be executed next?
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17.5. Instruction in the IR will:
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Load 3 to AC from the memory
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● Add 2 to AC from the memory
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● Store 3 to AC from the memory
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● Add 3 to AC from the memory
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17.6. Instruction in the IR will:
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● Load 3 to AC from the memory
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● Add 2 to AC from the memory
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● Store 3 to AC from the memory
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● Add 3 to AC from the memory
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17.7. Instruction in the IR will:
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● Store content of AC to the memory
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● Add 3 to the memory location from AC
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● Store 5 to AC from the memory
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● Add 2 to the memory location from AC
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17.8. What is the memory location of the data that is addressed in the instruction?
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17.9. What is the memory location of the data that is addressed in the instruction?
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17.10. What is the memory location of the data that is addressed in the
instruction?
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18. The fetched instruction is loaded into the
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● PC
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● Memory
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● Accumulator
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● IR
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19. At the beginning of each instruction cycle, the processor fetches an instruction
from the memory. The address of the instruction is held in
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20. The processor is executing ‘Load AC from memory’ instruction. Choose the
correct micro-instructions:
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● PC -> MAR
M -> MBR
MBR -> IR
IR -> MBR
M -> MAR
MAR -> AC
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● PC -> MAR
M -> MBR
MBR -> IR
IR -> MAR
M -> MBR
MBR -> AC
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● PC -> MBR
M -> MAR
MAR -> IR
IR -> MAR
M -> MBR
MBR -> AC
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● PC -> MAR
M -> MBR
MBR -> AC
IR -> MAR
M -> MBR
MBR -> AC
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21.1 Choose the micro-instructions that reflect instruction execution stage shown
in the figure below: (четыре вопроса в одном)четыре вопроса в одном))
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● PC -> MAR 303
M -> MBR 2941
MBR -> IR 2941
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● IR -> MAR 2941
AC -> MBR 0005
MBR -> M 0005
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● IR -> MAR 941
AC -> MBR 0005
MBR -> M 0005
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● IR -> MAR 303
M -> MBR 0005
MBR -> M 0005
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21.2 Choose true version?
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● IR -> MAR 941
M -> MBR 0002
MBR ->AC 0005
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● PC -> MAR 302
M -> MBR 2941
MBR -> IR 2941
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● IR -> MAR 941
M -> MBR 0002
MBR -> AC 0002
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● PC -> MAR 301
M -> I/OBR 5941
I/OBR 5941
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21.3 Choose true version?
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PC -> MAR 301
M -> MBR 6941
MBR -> IR 5941
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● IR -> MAR 941
AC -> MBR 0003
MBR -> M 0003
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● IR -> MAR 941
M -> MBR 0002
MBR -> AC 0002
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● PC -> MAR 301
M -> MBR 5941
MBR -> IR 5941
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Choose true version?
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● PC -> MAR 300
M -> MAR 1940
MBR -> IR 1940
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● PC -> MAR 300
M -> MBR 1940
MBR -> IR 1940
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● M -> MAR 300
M -> MBR 1940
MBR -> IR 1940
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● PC -> MAR 301
M -> MBR 1940
MBR -> IR 1940
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22. When an I/O device completes an I/O operation, the device issues an interrupt
signal to the processor and then:
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● The processor finishes execution of the current instruction before
responding to the interrupt
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● The processor saves information needed to resume the current program
at the point if interrupt
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● The processor loads the program counter with the entry location of the
interrupt-handling routine
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● The processor stops execution of the current instruction without finishing
it and responds to the interrupt
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23. When the time required for the I/O operation is less that the time to complete
the execution of instructions between write operations in the user program, it
is:
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● Short I/O wait
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● Long I/O wait
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● Slow I/O wait
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● Fast I/O wait
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24. When the time required for the I/O operation will take much more time than
executing a sequence of user instructions, it is:
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● Short I/O wait
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● Fast I/O wait
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● Long I/O wait
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● Slow I/O wait
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25. Most I/O devices are:
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26. If there no interrupts, after each write operation, the processor must:?????
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● Pause and remain idle until the I/O operation finishes
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● Save the PSW and PC onto control stack
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● Finish execution of current instruction
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● Load new PC value
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27. The processor determined that there is a pending interrupt and sent an
acknowledgement signal to the device that issued the interrupt. Then, the
processor:
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The processor tests for a pending interrupt request, determines that there is one, and
sends an acknowledgment signal to the device that issued the interrupt.The
acknowledgment allows the device to remove its interrupt signal
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жай гана ана сурактты зубри и все) Удачи
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28. The figure 1.5, 1.8, 1.9, 1.12, 1.13, 1.14, 1.19: (четыре вопроса в одном)м)ного вопросов в одном))
1. The following figure demonstrates:
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Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,2. The following figure demonstrates:
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Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,3. The following figure demonstrates:
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Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,4. The figure a) demonstrates the program timing diagram for:
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Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,5. The figure b) demonstrates the program timing diagram for
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● Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,6. The figure a) demonstrates the program timing diagram for:
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● Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,7. The figure b) demonstrates the program timing diagram for
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Interrupts; fast I/O wait
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● Interrupts; short I/O wait
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● Interrupts; long I/O wait
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● No interrupts
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● Interrupts; slow I/O wait
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28,8. The figure below shows
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Parallel interrupt processing
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● Nested interrupt processing
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● Sequential interrupt processing
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● Parent-child interrupt processing
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28,9. The figure below shows
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Parallel interrupt processing
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● Nested interrupt processing
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● Sequential interrupt processing
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● Parent-child interrupt processing
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28,10. The figure below shows
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Parallel interrupt processing
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● Nested interrupt processing
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● Sequential interrupt processing
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● Time Sequence of Multiple Interrupts
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28,11. As one goes down the memory hierarchy
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28,12. The given flowchart is an example of:
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28,13. The given flowchart is an example of:
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28,14. The given flowchart is an example of:
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29. Complete the relationship concerning the memory systems: faster access time
–
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● smaller cost per bit
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● faster access speed
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● greater cost per bit
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● lower capacity
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30. Complete the relationship concerning the memory systems: greater capacity –
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● smaller cost per bit
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● faster access speed
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● greater cost per bit
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● lower capacity
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31. Complete the relationship concerning the memory systems: greater capacity –
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● faster access speed
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● greater cost per bit
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● slower access time
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● lower capacity
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33. The smaller, more expensive, faster memory is:
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● Register
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● Main memory
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● Cache
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● Disk drive
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34. If the accessed word is found in the faster memory, that is defined as a:
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● evrika
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● hit
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● win
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● bingo
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35. If the accessed word is not found in the faster memory, that is defined as a:
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● Loss
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● zero
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● miss
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● ricochet
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36. This type of memory is nonvolatile:
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● Main memory
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● Cache
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● Secondary memory
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● Register