17514365
Descripción
Test por Last Quickly, actualizado hace más de 1 año
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Creado por Last Quickly
hace más de 5 años
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Pregunta 1
Pregunta
Out-of-Order Control Complexity MIPS R10000 which element is not in Control Logic?
Respuesta
-
Integer Datapath
-
CLK
-
Free List
-
Address Queue
Pregunta 2
Pregunta
What is “VLIW”?
Respuesta
-
Very Long Instruction Word
-
Very Less Interpreter Word
-
Very Light Internal Word
-
Very Low Invalid Word
Pregunta 3
Pregunta
At VLIW by “performance and loop iteration” which time is longer?
Respuesta
-
Loop Unrolled
-
Software Pipelined
Pregunta 4
Pregunta
At VLIW by “performance and loop iteration” which time is shorter?
Respuesta
-
Software Pipelined
-
Loop Unrolled
Pregunta 5
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem: Branches restrict compiler code motion?
Respuesta
-
Speculative operations that don’t cause exceptions
-
Hardware to check pointer hazards
Pregunta 6
Pregunta
At VLIW Speculative Execution, which of this solution is true about problem: Possible memory hazards limit code scheduling:
Respuesta
-
Hardware to check pointer hazards
-
Speculative operations that don’t cause exceptions
Pregunta 7
Pregunta
What is an ALAT? :
Respuesta
-
Advanced Load Address Table
-
Allocated Link Address Table
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Allowing List Address Table
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Addition Long Accessibility Table
Pregunta 8
Pregunta
At VLIW Multi-Way Branches, which of this solution is true about problem: Long instructions provide few opportunities for branches:
Respuesta
-
Allow one instruction to branch multiple directions
-
Speculative operations that don’t cause exceptions
Pregunta 9
Pregunta
What is a Compulsory?
Respuesta
-
first-reference to a block, occur even with infinite cache
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
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misses that occur because of collisions due to less than full associativity
Pregunta 10
Pregunta
What is a Capacity?
Respuesta
-
cache is too small to hold all data needed by program, occur even under perfect replacement policy
-
first-reference to a block, occur even with infinite cache
-
misses that occur because of collisions due to less than full associativity
Pregunta 11
Pregunta
Convert this number systems: DEC (9578) to HEX?
Respuesta
-
256A
-
43B1
-
7DE1
-
A31F
Pregunta 12
Pregunta
Convert this number systems: DEC (9845) to HEX?
Respuesta
-
2675
-
2798
-
2945
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2811
Pregunta 13
Pregunta
Define a boolean algebra
Respuesta
-
process that applies binary logic to yield binary results
-
to determine whether an IP address exists on the local network or whether it must be routed outside the local network.
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It sends out ICMP (Internet Control Message Protocol) messages to verify both the logical addresses & the Physical connection.
-
to determine whether an IP address exists on the global network or whether it must be routed outside the global network.
Pregunta 14
Pregunta
Where Virtual Machine was developed?
Respuesta
-
Lancaster University
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Manchester University
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MIT
-
Cambridge
Pregunta 15
Pregunta
What is the first commercial computer with virtual machine
Respuesta
-
B5000
-
B5550
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B5500
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C5000
Pregunta 16
Pregunta
When was the first commercial computer with virtual machine released?
Respuesta
-
1961
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1962
-
1963
-
1964
Pregunta 17
Pregunta
Which of the following is false about VM and performance?
Respuesta
-
Better performance: we can use more memory than we have
-
Nothing; mapping to memory or disk is just as easy
-
Worse performance: reading from disk is slower than RAM
-
Good performance: reading from disk is slower than RAM
Pregunta 18
Pregunta
Which of the following is false about usability of Virtual Memory?
Respuesta
-
Not enough memory
-
Holes in the address space
-
Keeping program secure
-
Keeping program insecure
Pregunta 19
Pregunta
Define virtual address space
Respuesta
-
process refers to the logical (or virtual) view of how a process is stored in memory
-
used to translate the virtual addresses seen by the application into physical addresses
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a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
-
none of the mentioned
Pregunta 20
Pregunta
Define a page tables
Respuesta
-
process refers to the logical (or virtual) view of how a process is stored in memory
-
used to translate the virtual addresses seen by the application into physical addresses
-
a segment of virtual memory that has been assigned a direct byte-for-byte correlation with some portion of a file or file-like resource.
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none of the mentioned
Pregunta 21
Pregunta
Of the following, identify the memory usually written by the manufacturer.
Respuesta
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RAM
-
DRAM
-
SRAM
-
ROM
-
Cache Memory
Pregunta 22
Pregunta
Multi-processor system that computer system have are also called
Respuesta
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parallel; systems
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tightly coupled system
-
loosely coupled system
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both a and b
Pregunta 23
Pregunta
Which of the following statement is false?
Respuesta
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Combinational circuits has memory
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Sequential circuits has memory
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Sequential circuits is a function of time
-
Combinational circuits does not require feedback paths
-
Sequential circuits require feedback paths.
Pregunta 24
Pregunta
The computer architecture having stored program is _____.
Respuesta
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Harvard
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Von-Neumann
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Pascal
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Ada
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Cobol
Pregunta 25
Pregunta
The key technology used in IV generation computers is _______.
Respuesta
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MSI
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SSI
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LSI &VLSI
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Transistors
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Vacuum Tubes
Pregunta 26
Pregunta
The digital circuit that generates the arithmetic sum of two binary numbers of any length is ________ .
Respuesta
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Binary-Adder
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Full-Adder
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Half-Adder
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Adder
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OR-gate
Pregunta 27
Pregunta
Serial to parallel data conversion is done using
Respuesta
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Accumulator
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Shift Register
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Counter
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CPU
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Control Unit
Pregunta 28
Pregunta
CACHE memory is implemented using ________.
Respuesta
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Dynamic RAM
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Static RAM
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EA RAM
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ED RAM
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EP RAM
Pregunta 29
Pregunta
Stack is a _________list.
Respuesta
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FIFO
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LIFO
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FILO
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OFLI
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LFIO.
Pregunta 30
Pregunta
Which one of the following is a memory whose duty is to store most frequently used data?
Respuesta
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Main memory
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Cache memory
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ROM
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Auxiliary memory
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PROM.
Pregunta 31
Pregunta
How many bytes equals Petabyte (PB)?
Respuesta
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Quadrillion
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Million
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Trillion
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Billion
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1000
Pregunta 32
Pregunta
Examples of superscalar(static):
Respuesta
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MIPS and ARM
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Pentium 4, MIPS R12K, IBM, Power5
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Itanium
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TI C6x
Pregunta 33
Pregunta
Examples of superscalar(dynamic) :
Respuesta
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None at the present
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Pentium 4, MIPS R12K, IBM, Power5
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MIPS and ARM
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TI C6x
Pregunta 34
Pregunta
How many main levels of Cache Memory?
Respuesta
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3
-
2
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6
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8
Pregunta 35
Pregunta
What is a “Synchronization” in OS Execution?
Respuesta
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Execution in the OS that is neither idle nor in synchronization access
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Execution in user code
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Execution or waiting for synchronization variables
Pregunta 36
Pregunta
What is a “Kernel” in OS Execution?
Respuesta
-
Execution or waiting for synchronization variables
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Execution in the OS that is neither idle nor in synchronization access
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Execution in user code
Pregunta 37
Pregunta
Which one of the following is correct?
Respuesta
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Sequential circuit is an interconnection of only logic gates
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Sequential circuit is an interconnection of only flip flops
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Combinational circuit is an interconnection of logic gates
-
Combinational circuit is an interconnection of flip flops
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Part of a combinational circuit is a sequential circuit.
Pregunta 38
Pregunta
Identify the expansion for RISC.
Respuesta
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Reduced Instruction Sign Computers
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Reduced Instruction Set Computers
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Reduced Instruction Set Carry
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Reduced Invalid Set Computers
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Reset Instruction Set Computers.
Pregunta 39
Pregunta
Buffering the actual target instructions allows us to perform an optimization which called:
Respuesta
-
branch folding
-
Branch prediction
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Target instructions
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Target address
Pregunta 40
Pregunta
Which is not the function of integrated instruction fetch unit:
Respuesta
-
Instruction memory commit
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Integrated branch prediction
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Instruction prefetch
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Instruction memory access and buffering
Pregunta 41
Pregunta
What is the simple technique that predicts whether two stores or a load and a store refer to the same memory address:
Respuesta
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Address aliasing prediction
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Branch prediction
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Integrated branch prediction
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Dynamic branch prediction
Pregunta 42
Pregunta
RISC stands for
Respuesta
-
Reduced Instruction Set Computer
-
Recall Instruction Sell Communication
-
Rename Instruction Sequence Corporation
-
Red Instruction Small Computer
Pregunta 43
Pregunta
The ideal pipeline CPI is a measure of …
Respuesta
-
the maximum performance attainable by the implementation
-
the maximum performance attainable by the instruction
-
the minimum performance attainable by the implementation
-
the minimum performance attainable by the instruction
Pregunta 44
Pregunta
What is the Pipeline CPI ?
Respuesta
-
Ideal pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
-
Ideal pipeline CPU + Data hazard stalls + Control stalls
-
Ideal pipeline CPU + Ideal pipeline CPI + Data hazard stalls + Control stalls
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Structural stalls + Data hazard stalls + Control stalls
Pregunta 45
Pregunta
The simplest and most common way to increase the ILP is …?
Respuesta
-
to exploit parallelism among iterations of a loop
-
to exploit minimalism among iterations of a loop
-
to destroy iterations of a loop
-
to decrease the minimalism of risk
Pregunta 46
Pregunta
The simplest and most common way to increase the ILP is to exploit parallelism among iterations of a loop. How is often called?
Respuesta
-
loop-level parallelism
-
exploit-level parallelism
-
high-level minimalism
-
low-level minimalism
Pregunta 47
Pregunta
In parallelism have three different types of dependences, tagging him:
Respuesta
-
data dependences, name dependences and control dependences
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data dependences, name dependences, and surname dependences
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datagram dependences ,name dependences, and animal dependences
-
no correct answers
Pregunta 48
Pregunta
What is Name dependence?
Respuesta
-
name dependence occurs when two instructions use the same register or memory location
-
name dependence occurs when five or more instructions use the same register or memory location
-
name dependence occurs when instructions use the same name
-
All answers is correct
Pregunta 49
Pregunta
When occurs an output dependence?
Respuesta
-
When i and instruction j write the same register or memory location
-
when i and instruction j write the same name
-
when i and instruction j write the same address or memory location
-
All answers is correct
Pregunta 50
Pregunta
What is RAW (read after write)?
Respuesta
-
when j tries to read a source before i writes it, so j incorrectly gets the old value
-
when i tries to read a source before j writes it, so j correctly gets the old value
-
when j tries to write a source before i writes it
-
when a tries to write a source before b read it, so a incorrectly gets the old value
Pregunta 51
Pregunta
What is given is not a hazard?
Respuesta
-
RAR
-
WAR
-
WAW
-
RAW
Pregunta 52
Pregunta
A simple scheme for increasing the number of instructions relative to the branch and overhead instructions is…?
Respuesta
-
loop unrolling
-
RAR
-
loop-level
-
loop rolling
Pregunta 53
Pregunta
Effect that results from instruction scheduling in large code segments is called…?
Respuesta
-
register pressure
-
loop unrolling
-
loop-level
-
registration
Pregunta 54
Pregunta
The simplest dynamic branch-prediction scheme is a
Respuesta
-
branch-prediction buffer
-
branch buffer
-
All answers correct
-
registration
Pregunta 55
Pregunta
Branch predictors that use the behavior of other branches to make a prediction are called
Respuesta
-
correlating predictors or two-level predictors
-
branch-prediction buffer
-
branch table
-
three level loop
Pregunta 56
Pregunta
What is the compulsory in Three C’s model?
Respuesta
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Pregunta 57
Pregunta
What is capacity in Three C’s model?
Respuesta
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
The number of accesses that miss divided by the number of accesses.
-
None of them
Pregunta 58
Pregunta
What is conflict in Three C’s model?
Respuesta
-
If the block placement strategy is not fully associative, conflict misses (in addition to compulsory and capacity misses) will occur because a block may be discarded and later retrieved if conflicting blocks map to its set
-
The very first access to a block cannot be in the cache, so the block must be brought into the cache. Compulsory misses are those that occur even if you had an infinite cache.
-
If the cache cannot contain all the blocks needed during execution of a program, capacity misses (in addition to compulsory misses) will occur because of blocks being discarded and later retrieved
-
None of them
Pregunta 59
Pregunta
Which of the following belongs to Cache Optimization?
Respuesta
-
Larger block size to reduce miss rate
-
Bigger caches to increase miss rat
-
Single level caches to reduce miss penalty
-
None of them
Pregunta 60
Pregunta
Choose the strategy of Sixth Cache Optimization
Respuesta
-
Critical word first
-
Critical restart
-
Sequential inter leaving
-
Merging Write Buffer to Reduce Miss Penalty
Pregunta 61
Pregunta
Choose the Seventh Cache Optimization
Respuesta
-
Merging Write Buffer to Reduce Miss Penalty
-
Critical word first
-
Nonblocking Caches to Increase Cache Bandwidth
-
Trace Caches to Reduce Hit Time
Pregunta 62
Pregunta
Choose the Tenth Cache Optimization
Respuesta
-
Compiler-Controlled Prefetching to Reduce Miss Penalty or Miss Rate
-
Merging Write Buffer to Reduce Miss Penalty
-
Hardware Prefetching of Instructions and Data to Reduce Miss Penalty or Miss Rate
-
None of them
Pregunta 63
Pregunta
What is the access time?
Respuesta
-
Time between when a read is requested and when the desired word arrives
-
The minimum time between requests to memory.
-
Describes the technology inside the memory chips and those innovative, internal organizations
-
None of them
Pregunta 64
Pregunta
What is the cycle time?
Respuesta
-
The minimum time between requests to memory.
-
Time between when a read is requested and when the desired word arrives
-
The maximum time between requests to memory.
-
None of them
Pregunta 65
Pregunta
What does DRAM stands for?
Respuesta
-
Dynamic Random Access memory
-
Dual Random Access memory
-
Dataram Random Access memory
Pregunta 66
Pregunta
What does DDR stands for?
Respuesta
-
Double data rate
-
Dual data rate
-
Double data reaction
-
None of them
Pregunta 67
Pregunta
What acts as the traffic cop controlling the flow of data and coordinating interactions among components in the system?
Respuesta
-
Microprocessor
-
Main memory
-
Storage device
-
Chipset
Pregunta 68
Pregunta
Instruction register stores_____________?
Respuesta
-
Data of the current instruction
-
Next Instruction which is to be executed
-
Address of the current instruction
-
Instruction which is currently executed
Pregunta 69
Pregunta
A Set of Physical Addresses is called ________________?
Respuesta
-
Pages
-
Address space
-
Disk space
-
Memory space
Pregunta 70
Pregunta
The ______________________ operation sets to 1 the bits in one register where there are corresponding?
Respuesta
-
Selective Clear
-
Mask
-
Selective Complement
-
Selective Set
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