3541315
Pregunta 1
Pregunta
Which of the following problems would NOT being identified during POST?
Respuesta
-
memory failure
-
bad monitor
-
bad video card
-
faulty CPU
Pregunta 2
Pregunta
In the figure below, Item D is the _______.
Respuesta
-
system board connections for IDE and floppy drives
-
DIMM slots
-
P1 power connection on the system board
-
PCI local bus slots
Pregunta 3
Pregunta
The correct order of the boot process is:
Respuesta
-
POST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
-
POST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
-
POST, OS configures the system and completes loading, User is able to execute application software
-
POST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS
Pregunta 4
Pregunta
What's the first thing the Startup BIOS looks for on a hard drive during boot up?
Respuesta
-
DOS Boot Record
-
Master Boot Record Correct
-
NT Boot Record
-
Piece of Pie
Pregunta 5
Pregunta
POST stands for:
Respuesta
-
partial operating system test
-
Power-off self test
-
Power-on self test
-
Pre-operational system test
-
None of the above
Pregunta 6
Pregunta
Which of the following is NOT a motherboard form factor:
Respuesta
-
ATX
-
Micro-PTX
-
LPX
-
BTX
-
AT
Pregunta 7
Pregunta
Which statement is NOT true about CMOS chips:
Respuesta
-
They maintain their settings long after you remove the CMOS battery
-
They generally hold between 64 bytes and 512 bytes of memory
-
They are sometimes referred to as NVRAM
-
They contain resource settings for plug-and-play devices in the ESCD
-
They contain the Real Time Clock that holds PC's time and date settings
Pregunta 8
Pregunta
How many of the following components are part of the CPU?
• ALU
• Real Time Clock
• branch predictor
• Registers
• Program Counter
Respuesta
-
1
-
2
-
3
-
4
-
5
Pregunta 9
Pregunta
Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?
Respuesta
-
Doubler and Tripler clocks
-
Derived System Clocks
-
Multiplier and Divider Clocks
-
Frequency Multiplexers
Pregunta 10
Pregunta
Which term is commonly used to reference the process of division and
multiplication of the system clock to achieve the desired frequency?
Respuesta
-
Doubler and Tripler clocks
-
Derived System Clocks
-
Multiplier and Divider clocks
-
Frequency Multiplexers
Pregunta 11
Pregunta
Secondary cache, also called ______ cache, may be located either in the
CPU cartridge or on the system board near the CPU.
Respuesta
-
L1
-
L2
-
L3
-
L4
Pregunta 12
Pregunta
How many of the following items are true regarding cache?
◦ Cache uses DRAM with is faster that SRAM (found in main memory)
◦ Cache is not always found in the CPU
◦ Cache is designed as temporary storage for the CPU
◦ The size of cache is matched to be equal to the amount of main memory in
the computer
Respuesta
-
0
-
1
-
2
-
3
-
4
Pregunta 13
Pregunta
Early Pentium CPUs are said to have multi-processing capabilities because they ____________
Respuesta
-
Can process data coming in while sending data out
-
Have the ability to exist with other processors
-
Use multiple registers
-
Contain two Arithmetic Logic Units Correct
Pregunta 14
Pregunta
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
Respuesta
-
L4
-
L3
-
L2
-
L1
Pregunta 15
Pregunta
Different speeds for computer components are achieved by using what is called ___________.
Respuesta
-
Frequency Multiplexers
-
Multiplier and Divider clocks
-
Derived System Clocks
-
Doubler and Tripler clocks
Pregunta 16
Pregunta
Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.
Respuesta
-
I/O Controller Hub
-
ISA bus
-
Graphics Memory Controller Hub
-
South Bridge
Pregunta 17
Pregunta
The amount of addressable memory is determined by the size of the address bus.
Respuesta
- True
- False
Pregunta 18
Pregunta
The Multiplier is the term used to describe the ________________
Respuesta
-
the ratio of the Backside Bus speed to the Memory Bus speed
-
the ratio of the Backside Bus speed to the CPU operating speed
-
the ratio of the CPU operating speed to the Front Side Bus speed
-
the ratio of the PCI bus speed to the Memory Bus speed
Pregunta 19
Pregunta
The front side bus connects the CPU to the ______.
Respuesta
-
coprocessor
-
L1 cache
-
system clock
-
memory bus
Pregunta 20
Pregunta
A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump
Respuesta
-
Control Unit
-
Branch Predictor
-
Hyper-Threading Technology
-
Cache
Pregunta 21
Pregunta
A unit that controls the operations of all components in the processor and executes conditional instructions
Respuesta
-
control unit
-
Instruction Register
-
Branch Predictor
-
ALU
Pregunta 22
Pregunta
Allows access to the hard disk drive, USB ports and other I/O devices
Respuesta
-
Cache
-
Program Counter
-
North Bridge
-
South Bridge
Pregunta 23
Pregunta
Allows access to the RAM and video card
Respuesta
-
North Bridge
-
South Bridge
-
West Bridge
-
East Bridge
Pregunta 24
Pregunta
A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel
Respuesta
-
Cache
-
Arithmetic Logic Unit
-
Hyper-Threading Technology
-
Superscalar Architecture
Pregunta 25
Pregunta
An internal memory location that contrains the instruction that is to be executed.
Respuesta
-
Cache
-
Instruction Register
-
Branch Predictor
-
South Bridge
Pregunta 26
Pregunta
The part of the CPU that processes arithmetic and logical instructions
Respuesta
-
Floating Point Unit
-
Arithmetic Logic Unit
-
Multiplier Bus
-
Divisor Programming Unit
Pregunta 27
Pregunta
An internal memory location that contains the address of the next instruction to be executed
Respuesta
-
Counting Register
-
Address Bus Architecture
-
Address Memory Unit
-
Program Counter
Pregunta 28
Pregunta
Used as temporary storage for the CPU
Respuesta
-
RAM
-
ROM
-
Cache
-
Hard Disk Drive
Pregunta 29
Pregunta
The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.
Respuesta
-
DMA Controller
-
IRQ Controller
-
Chipset
-
Super I/O
Pregunta 30
Pregunta
Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)
Respuesta
-
ISA
-
System
-
AGP
-
Memory
-
VESA-Local Bus
-
PCI
Pregunta 31
Pregunta
With 486 and higher CPUs, the cache controller is ________.
Respuesta
-
attached to the CMOS chip
-
not required, as the CPU itself controls the cache
-
housed on the system board
-
embedded in the CPU chip
Pregunta 32
Pregunta
Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.
Respuesta
-
Fast Bridge
-
ICH
-
North Bridge
-
South Bridge
Pregunta 33
Pregunta
Which of the following items relieves the CPU of processing traffic to
and from all the buses and controllers on the system board?
Respuesta
-
IRQ Controller
-
Chipset
-
DMA Controller
-
Super I/O
Pregunta 34
Pregunta
The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.
Respuesta
-
South Bridge
-
North Bridge
-
ICH
-
East Bridge
-
West Bridge
Pregunta 35
Pregunta
How many of the following buses connect to the GMCH in the
Accelerated Hub Architecture Chipset?
•PCI • System
• Memory • AGP
• ISA • VESA-Local Bus
Respuesta
-
1
-
2
-
3
-
4
-
5
Pregunta 36
Pregunta
Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.
Respuesta
-
356
-
504
-
768
-
943
Pregunta 37
Pregunta
A SCSI chain must be terminated either by a passive, active or forced perfect terminator.
Respuesta
- True
- False
Pregunta 38
Pregunta
With IDE drives, the OS executes the remainder of the format process. This is known as a _____.
Select one:
Respuesta
-
low level format
-
high-level format
-
partition
-
part
Pregunta 39
Pregunta
Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.
Respuesta
- True
- False
Pregunta 40
Pregunta
Which SCSI ID would usually be used for Hard Drives?
Respuesta
-
0
-
2
-
4
-
7
Pregunta 41
Pregunta
In a process called _____, track and sector markings are written on the hard drive at the factory.
Respuesta
-
high-level formatting
-
low level formatting
-
partitioning
-
parking
Pregunta 42
Pregunta
IDE drives use a _____-pin cable.
Respuesta
-
34
-
40
-
50
-
68
Pregunta 43
Pregunta
LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.
Respuesta
- True
- False
Pregunta 44
Pregunta
What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?
Respuesta
-
Parallel ATA
-
Serial ATA
-
Synchronous ATA
-
Single Mode ATA
Pregunta 45
Pregunta
Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.
Respuesta
- True
- False
Pregunta 46
Pregunta
Zone Bit Recording means ___________________
Respuesta
-
the number of sectors/track vary depending on the location of the track.
-
the tracks are arranged so the same number of sectors are used for all tracks.
-
each bit is recorded one zone at a time
-
a type of logical method of addressing larger capacity drives
Pregunta 47
Pregunta
Serial ports transmit data one byte at a time.
Respuesta
- True
- False
Pregunta 48
Pregunta
Which of the following is NOT a type of parallel port?
Respuesta
-
SPP
-
EPP
-
ECP
-
EDP
Pregunta 49
Pregunta
Parallel ports transmit data in parallel, _____ bit(s) at a time.
Respuesta
-
1
-
2
-
4
-
8
Pregunta 50
Pregunta
When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.
Respuesta
-
Normal
-
LBA
-
CHS
-
ECHS
Pregunta 51
Pregunta
Which of the following is true about SCSI vs EIDE?
Respuesta
-
EIDE is harder to set up than SCSI
-
SCSI is faster and more expensive
-
EIDE is faster and more expensive
-
SCSI is more popular than EIDE
Pregunta 52
Pregunta
The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?
Respuesta
-
504 MB
-
7.88 Gbits
-
128 GB
-
7.88 GB
Pregunta 53
Pregunta
In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.
Respuesta
-
adapter
-
ROM bios
-
CMOS chip
-
controller
Pregunta 54
Pregunta
The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.
Respuesta
-
actuators
-
heads
-
platters
-
spindles
Pregunta 55
Pregunta
A null-modem cable can be used to directly connect two ____ devices.
Respuesta
-
DTE
-
DCE
-
DCA
-
DMA
Pregunta 56
Pregunta
Which statement is NOT true about CMOS chips:
Respuesta
-
They maintain their settings long after you remove the CMOS battery
-
They generally hold between 64 bytes and 512 bytes of memory
-
They are sometimes referred to as NVRAM
-
They contain resource settings for plug-and-play devices in the ESCD (Extended System Configuration Data) area
-
The contain the Real Time Clock that holds the PC’s time and date settings
Pregunta 57
Pregunta
The fast end of the Chipset Hub Architecture is still often referred to as
the hub's ________.
Respuesta
-
South Bridge
-
North Bridge
-
ICH
-
East Bridge
-
West Bridge
Pregunta 58
Pregunta
Parallel ports are only able to transmit data in one direction at any given
time.
Respuesta
- True
- False
Pregunta 59
Pregunta
Synchronous memory requires an external clock signal while
Asynchronous does not.
Respuesta
- True
- False
Pregunta 60
Pregunta
How many of the following statements are true?
◦ DRAM is always faster that SRAM
◦ SRAM is lower cost that DRAM
◦ Both DRAM and SRAM are available in synchronous and asynchronous forms
◦ Both SRAM and DRAM retains values when the power is off
Respuesta
-
0
-
1
-
2
-
3
-
4
Pregunta 61
Pregunta
How many of the following statements are true?
◦ DRAM does not require refreshing to hold data
◦ SRAM allows for faster data access that DRAM
◦ SRAM costs more than DRAM per byte
◦ SRAM and DRAM memory cells are the same physical size per byte
Respuesta
-
0
-
1
-
2
-
3
-
4
Pregunta 62
Pregunta
How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors
Respuesta
-
0
-
1
-
2
-
3
-
4
Pregunta 63
Pregunta
How many of the following statements are true?
◦ ECC and non-ECC memory cost the same
◦ The parity bit in parity memory can be used to reconstruct bad data
◦ ECC memory allows for the correction of single bit errors
◦ Non-parity memory can detect and correct memory errors
Respuesta
-
Even
-
Odd
Pregunta 64
Pregunta
Which BUS version is set to replace AGP?
Respuesta
-
PCIe
-
ISA
-
Infiniband
-
PCI-X
Pregunta 65
Pregunta
With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.
Respuesta
- True
- False
Pregunta 66
Pregunta
Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.
Respuesta
- True
- False
Pregunta 67
Pregunta
What kind of Parity checking is being used if the following byte of data and it's parity bit are correct:
Value: 1011 0111 Parity Bit: 1
Respuesta
-
even
-
equal
-
odd
-
balanced
Pregunta 68
Pregunta
Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.
Respuesta
-
PRAM, DRAM
-
SRAM, DRAM
-
DRAM, SRAM
-
SRAM, PRAM
Pregunta 69
Pregunta
What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?
Respuesta
-
Ram Timing Detect
-
Auto-Timing Detect
-
Serial Presence Detect
-
Memory Alert
Pregunta 70
Pregunta
Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.
Respuesta
- True
- False
Pregunta 71
Pregunta
You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?
Respuesta
-
1.6GB/s
-
2.1GB/s
-
3.2GB/s
-
1.06GB/s
Pregunta 72
Pregunta
One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.
Respuesta
-
checksum
-
bit parity
-
ESCD
-
PRAM
Pregunta 73
Pregunta
What type of bus is displayed in the figure below
Respuesta
-
16-bit ISA
-
VESA
-
8-bit ISA
-
PCI
Pregunta 74
Pregunta
The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus.
(HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)
Respuesta
-
6,3
-
3,6
-
5,3
-
5,4
Pregunta 75
Pregunta
Which of the following is a list of expansion bus types ?
Respuesta
-
MCA, PCI, Memory
-
ISA, EISA
-
ISA, PCD, AGD
-
PCI, DIMM, SIMM
Pregunta 76
Pregunta
The ______ ISA bus was so named because it had only an eight-bit data path.
Respuesta
-
4-bit
-
8-bit
-
16-bit
-
32-bit
Pregunta 77
Pregunta
ECC may be present on DIMM module, and correct single bit errors when possible.
Respuesta
- True
- False
Pregunta 78
Pregunta
DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.
Respuesta
- True
- False
Pregunta 79
Pregunta
Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.
Respuesta
-
even
-
equal
-
odd
-
balanced
Pregunta 80
Pregunta
All data stored in _____ is lost when the power is turned off.
Respuesta
-
PRAM
-
RAM
-
ROM
-
CMOS
Pregunta 81
Pregunta
On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)
Respuesta
-
2.1 GB/s
-
1.6 GB/s
-
500 MB/s
-
3.2 GB/s
Pregunta 82
Pregunta
The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.
Respuesta
-
S-100
-
8-bit ISA
-
16-bit ISA
-
EISA
Pregunta 83
Pregunta
ECC RAM differs from parity and nonparity RAM in that it can ______.
Respuesta
-
retain data when the power is removed
-
detect errors
-
automatically save data to the hard drive
-
detect and potentially correct errors
¿Quieres crear tus propios Tests gratis con GoConqr? Más información.