3827442
Description
Mind Map by Cristina Pérez9355, updated more than 1 year ago
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Created by Cristina Pérez9355
about 9 years ago
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Vhdl source file
- synthesis
- circuit synthesized for a target chip
PDL, FPGA
- VHDL-based simulation
TestBench
- behavioral high-level simulation
- Gate-level simulation
- Run simulation
- Run simulation
- behavioral high-level simulation
- LAB test & measurements
- VHDL-based simulation
TestBench
- circuit synthesized for a target chip
PDL, FPGA
- Circuit_1.vhd
- writing a text file
scriptum editor
- equation
- equation
- schematic entry
translation
- schematic
- schematic
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