13904895
Descrição
Quiz por Good Guy Beket, atualizado more than 1 year ago
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Criado por Good Guy Beket
mais de 6 anos atrás
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Questão 1
Questão
What is a Latency:
Responda
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is time for a single access – Main memory latency is usually >> than processor cycle time
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is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
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is amount of data that can be in flight at the same time (Little’s Law)
Questão 2
Questão
What occurs at Intruction fetches when we speak about Common And Predictable Memory Reference Patterns?
Responda
-
n loop iterations
-
subroutine call
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vector access
Questão 3
Questão
What occurs at Stack access when we speak about Common And Predictable Memory Reference Patterns?
Responda
-
subroutine call
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n loop iterations
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vector access
Questão 4
Questão
What occurs at Data access when we speak about Common And Predictable Memory Reference Patterns?
Responda
-
subroutine call
-
n loop iterations
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vector access
Questão 5
Questão
Cache HIT:
Responda
-
No Write Allocate, Write Allocate
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Write Through, Write Back
Questão 6
Questão
Cache MISS:
Responda
-
No Write Allocate, Write Allocate
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Write Through, Write Back
Questão 7
Questão
Average Memory Access Time is equal:
Responda
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Hit Time * ( Miss Rate + Miss Penalty )
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Hit Time - ( Miss Rate + Miss Penalty )
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Hit Time / ( Miss Rate - Miss Penalty )
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Hit Time + ( Miss Rate * Miss Penalty )
Questão 8
Questão
The formula of “Iron Law” of Processor Performance:
Responda
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time/program = instruction/program * cycles/instruction * time/cycle
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time/program = instruction/program * cycles/instruction + time/cycle
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time/program = instruction/program + cycles/instruction * time/cycle
Questão 9
Questão
Structural Hazard:
Responda
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An instruction in the pipeline needs a resource being used by another instruction in the pipeline
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An instruction depends on a data value produced by an earlier instruction
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Questão 10
Questão
Data Hazard:
Responda
-
An instruction depends on a data value produced by an earlier instruction
-
An instruction in the pipeline needs a resource being used by another instruction in the pipeline
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
Questão 11
Questão
Control Hazard:
Responda
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Whether or not an instruction should be executed depends on a control decision made by an earlier instruction
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An instruction depends on a data value produced by an earlier instruction
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An instruction in the pipeline needs a resource being used by another instruction in the pipeline
Questão 12
Questão
What is a Bandwidth:
Responda
-
a is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
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is time for a single access – Main memory latency is usually >> than processor cycle time
-
is amount of data that can be in flight at the same time (Little’s Law)
Questão 13
Questão
What is a Bandwidth-Delay Product:
Responda
-
is amount of data that can be in flight at the same time (Little’s Law)
-
is time for a single access – Main memory latency is usually >> than processor cycle time
-
is the number of accesses per unit time – If m instructions are loads/stores, 1 + m memory accesses per instruction, CPI = 1 requires at least 1 + m memory accesses per cycle
Questão 14
Questão
What is Computer Architecture?
Responda
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is the design of the abstraction/implementation layers that allow us to execute information processing applications efficiently using manufacturing technologies
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is a group of computer systems and other computing hardware devices that are linked together through communication channels to facilitate communication and resource-sharing among a wide range of users
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the programs used to direct the operation of a computer, as well as documentation giving instructions on how to use them
Questão 15
Questão
Least Recently Used (LRU):
Responda
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cache state must be updated on every access
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Used in highly associative caches
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FIFO with exception for most recently used block(s)
Questão 16
Questão
Cache Hit -
Responda
-
Write Through – write both cache and memory, generally higher traffic but simpler to design
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Write cache only, memory is written when evicted, dirty bit per block avoids unnecessary write backs, more complicated
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No Write Allocate – only write to main memory
Questão 17
Questão
Reduce Miss Rate: Large Cache Size.
Empirical Rule of Thumb:
Responda
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If cache size is doubled, miss rate usually drops by about √2
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Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
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None of them
Questão 18
Questão
Reduce Miss Rate: High Associativity.
Empirical Rule of Thumb:
Responda
-
Direct-mapped cache of size N has about the same miss rate as a two-way set- associative cache of size N/2
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If cache size is doubled, miss rate usually drops by about √2
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None of them
Questão 19
Questão
What is the access time?
Responda
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Time between when a read is requested and when the desired word arrives
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The minimum time between requests to memory.
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Describes the technology inside the memory chips and those innovative, internal organizations
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None of them
Questão 20
Questão
What is the cycle time?
Responda
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The minimum time between requests to memory.
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Time between when a read is requested and when the desired word arrives
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The maximum time between requests to memory.
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None of them
Questão 21
Questão
What does SRAM stands for?
Responda
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Static Random Access memory
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System Random Access memory
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Short Random Access memory
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None of them
Questão 22
Questão
What does DRAM stands for?
Responda
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Dynamic Random Access memory
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Dual Random Access memory
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Dataram Random Access memory
Questão 23
Questão
Which one is concerning to fallacy?
Responda
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Predicting cache performance of one program from another
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Simulating enough instructions to get accurate performance measures of the memory hierarchy
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Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
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Over emphasizing memory bandwidth in DRAMs
Questão 24
Questão
Which one is NOT concerning to pitfall?
Responda
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Predicting cache performance of one program from another
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Simulating enough instructions to get accurate performance measures of the memory hierarchy
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Implementing a virtual machine monitor on an instruction set architecture that wasn’t designed to be virtualizable
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Over emphasizing memory bandwidth in DRAMs
Questão 25
Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “System response time” - ?
Responda
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The time between when the user enters the command and the complete response is displayed
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The time for the user to enter the command
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The time from the reception of the response until the user begins to enter the next command
Questão 26
Questão
If we talk about storage systems an interaction or transaction with a computer is divided for first what is an “Think time” - ?
Responda
-
The time from the reception of the response until the user begins to enter the next command
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The time for the user to enter the command
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The time between when the user enters the command and the complete response is displayed
Questão 27
Questão
Little’s Law and a series of definitions lead to several useful equations for “Time server” -
Responda
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
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Average time per task in the queue
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Questão 28
Questão
Little’s Law and a series of definitions lead to several useful equations for “Time queue” -
Responda
-
Average time per task in the queue
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
Questão 29
Questão
Little’s Law and a series of definitions lead to several useful equations for “Time system” -
Responda
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Average time/task in the system, or the response time, which is the sum of Time queue and Time server
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Average time to service a task; average service rate is 1/Time server traditionally represented by the symbol µ in many queuing texts
-
Average time per task in the queue
Questão 30
Questão
Little’s Law and a series of definitions lead to several useful equations for “Length server” -
Responda
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Average number of tasks in service
-
Average length of queue
Questão 31
Questão
Little’s Law and a series of definitions lead to several useful equations for “Length queue” -
Responda
-
Average length of queue
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Average number of tasks in service
Questão 32
Questão
Select two-dimensional interconnection network
Responda
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Mesh
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Linear Array
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Cross Bar
Questão 33
Questão
Select multi-dimensional interconnection network
Responda
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Linear Array
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Cross Bar
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Cube
Questão 34
Questão
Select multi-dimensional interconnection network
Responda
-
Linear Array
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Cross Bar
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Hyper Cube
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