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NTEN 111 - Midterm 1 Study Guide

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Preperation for NTEN 111 at Okanagan College (2015, Berg)
j.salvino
Quiz by j.salvino, updated more than 1 year ago
j.salvino
Created by j.salvino over 9 years ago
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Resource summary

Question 1

Question
Which of the following problems would NOT being identified during POST?
Answer
  • memory failure
  • bad monitor
  • bad video card
  • faulty CPU

Question 2

Question
In the figure below, Item D is the _______.
Image:
55b444a2-1fee-4466-94d9-b4ad0773de09 (image/jpeg)
Answer
  • system board connections for IDE and floppy drives
  • DIMM slots
  • P1 power connection on the system board
  • PCI local bus slots

Question 3

Question
The correct order of the boot process is:
Answer
  • POST, User is able to execute application software, ROM BIO searches for and loads OS, OS configures the system and completes loading
  • POST, ROM BIO searches for and loads OS, OS configures the system and completes loading, User is able to execute application software
  • POST, OS configures the system and completes loading, User is able to execute application software
  • POST, User is able to execute application software, OS configures the system and completes loading, ROM BIO searches for and loads OS

Question 4

Question
What's the first thing the Startup BIOS looks for on a hard drive during boot up?
Answer
  • DOS Boot Record
  • Master Boot Record Correct
  • NT Boot Record
  • Piece of Pie

Question 5

Question
POST stands for:
Answer
  • partial operating system test
  • Power-off self test
  • Power-on self test
  • Pre-operational system test
  • None of the above

Question 6

Question
Which of the following is NOT a motherboard form factor:
Answer
  • ATX
  • Micro-PTX
  • LPX
  • BTX
  • AT

Question 7

Question
Which statement is NOT true about CMOS chips:
Answer
  • They maintain their settings long after you remove the CMOS battery
  • They generally hold between 64 bytes and 512 bytes of memory
  • They are sometimes referred to as NVRAM
  • They contain resource settings for plug-and-play devices in the ESCD
  • They contain the Real Time Clock that holds PC's time and date settings

Question 8

Question
How many of the following components are part of the CPU? • ALU • Real Time Clock • branch predictor • Registers • Program Counter
Answer
  • 1
  • 2
  • 3
  • 4
  • 5

Question 9

Question
Which is commonly used to reference the process of division and multiplication of the system clock achieve the desired frequency?
Answer
  • Doubler and Tripler clocks
  • Derived System Clocks
  • Multiplier and Divider Clocks
  • Frequency Multiplexers

Question 10

Question
Which term is commonly used to reference the process of division and multiplication of the system clock to achieve the desired frequency?
Answer
  • Doubler and Tripler clocks
  • Derived System Clocks
  • Multiplier and Divider clocks
  • Frequency Multiplexers

Question 11

Question
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
Answer
  • L1
  • L2
  • L3
  • L4

Question 12

Question
How many of the following items are true regarding cache? ◦ Cache uses DRAM with is faster that SRAM (found in main memory) ◦ Cache is not always found in the CPU ◦ Cache is designed as temporary storage for the CPU ◦ The size of cache is matched to be equal to the amount of main memory in the computer
Answer
  • 0
  • 1
  • 2
  • 3
  • 4

Question 13

Question
Early Pentium CPUs are said to have multi-processing capabilities because they ____________
Answer
  • Can process data coming in while sending data out
  • Have the ability to exist with other processors
  • Use multiple registers
  • Contain two Arithmetic Logic Units Correct

Question 14

Question
Secondary cache, also called ______ cache, may be located either in the CPU cartridge or on the system board near the CPU.
Answer
  • L4
  • L3
  • L2
  • L1

Question 15

Question
Different speeds for computer components are achieved by using what is called ___________.
Answer
  • Frequency Multiplexers
  • Multiplier and Divider clocks
  • Derived System Clocks
  • Doubler and Tripler clocks

Question 16

Question
Which part of the Accelerated Hub Architecture chipset does the Memory bus connect to on modern system boards.
Answer
  • I/O Controller Hub
  • ISA bus
  • Graphics Memory Controller Hub
  • South Bridge

Question 17

Question
The amount of addressable memory is determined by the size of the address bus.
Answer
  • True
  • False

Question 18

Question
The Multiplier is the term used to describe the ________________
Answer
  • the ratio of the Backside Bus speed to the Memory Bus speed
  • the ratio of the Backside Bus speed to the CPU operating speed
  • the ratio of the CPU operating speed to the Front Side Bus speed
  • the ratio of the PCI bus speed to the Memory Bus speed

Question 19

Question
The front side bus connects the CPU to the ______.
Answer
  • coprocessor
  • L1 cache
  • system clock
  • memory bus

Question 20

Question
A unit that attempts to guess which instruction will be executed next when the processor encouters a conditional jump
Answer
  • Control Unit
  • Branch Predictor
  • Hyper-Threading Technology
  • Cache

Question 21

Question
A unit that controls the operations of all components in the processor and executes conditional instructions
Answer
  • control unit
  • Instruction Register
  • Branch Predictor
  • ALU

Question 22

Question
Allows access to the hard disk drive, USB ports and other I/O devices
Answer
  • Cache
  • Program Counter
  • North Bridge
  • South Bridge

Question 23

Question
Allows access to the RAM and video card
Answer
  • North Bridge
  • South Bridge
  • West Bridge
  • East Bridge

Question 24

Question
A processor design where the circuitry for each stage of the pipeline is duplicated to allow multiple instructions to pass through in parallel
Answer
  • Cache
  • Arithmetic Logic Unit
  • Hyper-Threading Technology
  • Superscalar Architecture

Question 25

Question
An internal memory location that contrains the instruction that is to be executed.
Answer
  • Cache
  • Instruction Register
  • Branch Predictor
  • South Bridge

Question 26

Question
The part of the CPU that processes arithmetic and logical instructions
Answer
  • Floating Point Unit
  • Arithmetic Logic Unit
  • Multiplier Bus
  • Divisor Programming Unit

Question 27

Question
An internal memory location that contains the address of the next instruction to be executed
Answer
  • Counting Register
  • Address Bus Architecture
  • Address Memory Unit
  • Program Counter

Question 28

Question
Used as temporary storage for the CPU
Answer
  • RAM
  • ROM
  • Cache
  • Hard Disk Drive

Question 29

Question
The ___________ contains a group of secondary chips that relieves the CPU of processing traffic to and from all the buses and controllers on the system board.
Answer
  • DMA Controller
  • IRQ Controller
  • Chipset
  • Super I/O

Question 30

Question
Which three Buses connect to the GMCH in the Accelerated Hub Architecture Chipset design developed by Intel ? (Select three)
Answer
  • ISA
  • System
  • AGP
  • Memory
  • VESA-Local Bus
  • PCI

Question 31

Question
With 486 and higher CPUs, the cache controller is ________.
Answer
  • attached to the CMOS chip
  • not required, as the CPU itself controls the cache
  • housed on the system board
  • embedded in the CPU chip

Question 32

Question
Although different manufacturers may refer it with different proprietary names, the fast end of the Chipset Hub Architecture is still commonly referred to as the hub's ________.
Answer
  • Fast Bridge
  • ICH
  • North Bridge
  • South Bridge

Question 33

Question
Which of the following items relieves the CPU of processing traffic to and from all the buses and controllers on the system board?
Answer
  • IRQ Controller
  • Chipset
  • DMA Controller
  • Super I/O

Question 34

Question
The fast end of the Chipset Hub Architecture is still often referred to as the hub's ________.
Answer
  • South Bridge
  • North Bridge
  • ICH
  • East Bridge
  • West Bridge

Question 35

Question
How many of the following buses connect to the GMCH in the Accelerated Hub Architecture Chipset? •PCI • System • Memory • AGP • ISA • VESA-Local Bus
Answer
  • 1
  • 2
  • 3
  • 4
  • 5

Question 36

Question
Early IDE drives followed the IDE/ATA (Integrated Device Electronics AT Attachment) standard which used CHS mode translation and limited drive size to _____ Megabytes.
Answer
  • 356
  • 504
  • 768
  • 943

Question 37

Question
A SCSI chain must be terminated either by a passive, active or forced perfect terminator.
Answer
  • True
  • False

Question 38

Question
With IDE drives, the OS executes the remainder of the format process. This is known as a _____. Select one:
Answer
  • low level format
  • high-level format
  • partition
  • part

Question 39

Question
Beginning with IDE technology, the number of sectors per track varied depending on the location of the track.
Answer
  • True
  • False

Question 40

Question
Which SCSI ID would usually be used for Hard Drives?
Answer
  • 0
  • 2
  • 4
  • 7

Question 41

Question
In a process called _____, track and sector markings are written on the hard drive at the factory.
Answer
  • high-level formatting
  • low level formatting
  • partitioning
  • parking

Question 42

Question
IDE drives use a _____-pin cable.
Answer
  • 34
  • 40
  • 50
  • 68

Question 43

Question
LBA, or logical block addressing, is the most suitable translation mode for large capacity drives in use today.
Answer
  • True
  • False

Question 44

Question
What newer technology is being used to replace the 40 pin ribbon cables that have been used in the past for Hard Drives?
Answer
  • Parallel ATA
  • Serial ATA
  • Synchronous ATA
  • Single Mode ATA

Question 45

Question
Low level formatting of an IDE drive could permanently destroy the drive data and render the drive unusable.
Answer
  • True
  • False

Question 46

Question
Zone Bit Recording means ___________________
Answer
  • the number of sectors/track vary depending on the location of the track.
  • the tracks are arranged so the same number of sectors are used for all tracks.
  • each bit is recorded one zone at a time
  • a type of logical method of addressing larger capacity drives

Question 47

Question
Serial ports transmit data one byte at a time.
Answer
  • True
  • False

Question 48

Question
Which of the following is NOT a type of parallel port?
Answer
  • SPP
  • EPP
  • ECP
  • EDP

Question 49

Question
Parallel ports transmit data in parallel, _____ bit(s) at a time.
Answer
  • 1
  • 2
  • 4
  • 8

Question 50

Question
When the hard drive BIOS communicates with the system BIOS in a translation method unrelated to cylinders, heads and sectors, _______ mode is being used.
Answer
  • Normal
  • LBA
  • CHS
  • ECHS

Question 51

Question
Which of the following is true about SCSI vs EIDE?
Answer
  • EIDE is harder to set up than SCSI
  • SCSI is faster and more expensive
  • EIDE is faster and more expensive
  • SCSI is more popular than EIDE

Question 52

Question
The IDE/ATA standard for a hard drive set the maximum values for Cylinders/Heads/Sectors to be 65,536/16/256. Based on this CHS calculation, what will be the maximum hard drive capacity allowed?
Answer
  • 504 MB
  • 7.88 Gbits
  • 128 GB
  • 7.88 GB

Question 53

Question
In IDE and SCSI drives, a(n) _____ is mounted on a circuit board on the drive housing and is an integral part of the drive.
Answer
  • adapter
  • ROM bios
  • CMOS chip
  • controller

Question 54

Question
The number of sides or surfaces of hard drive platters contained in a hard disk is also referred to as the number of _____.
Answer
  • actuators
  • heads
  • platters
  • spindles

Question 55

Question
A null-modem cable can be used to directly connect two ____ devices.
Answer
  • DTE
  • DCE
  • DCA
  • DMA

Question 56

Question
Which statement is NOT true about CMOS chips:
Answer
  • They maintain their settings long after you remove the CMOS battery
  • They generally hold between 64 bytes and 512 bytes of memory
  • They are sometimes referred to as NVRAM
  • They contain resource settings for plug-and-play devices in the ESCD (Extended System Configuration Data) area
  • The contain the Real Time Clock that holds the PC’s time and date settings

Question 57

Question
The fast end of the Chipset Hub Architecture is still often referred to as the hub's ________.
Answer
  • South Bridge
  • North Bridge
  • ICH
  • East Bridge
  • West Bridge

Question 58

Question
Parallel ports are only able to transmit data in one direction at any given time.
Answer
  • True
  • False

Question 59

Question
Synchronous memory requires an external clock signal while Asynchronous does not.
Answer
  • True
  • False

Question 60

Question
How many of the following statements are true? ◦ DRAM is always faster that SRAM ◦ SRAM is lower cost that DRAM ◦ Both DRAM and SRAM are available in synchronous and asynchronous forms ◦ Both SRAM and DRAM retains values when the power is off
Answer
  • 0
  • 1
  • 2
  • 3
  • 4

Question 61

Question
How many of the following statements are true? ◦ DRAM does not require refreshing to hold data ◦ SRAM allows for faster data access that DRAM ◦ SRAM costs more than DRAM per byte ◦ SRAM and DRAM memory cells are the same physical size per byte
Answer
  • 0
  • 1
  • 2
  • 3
  • 4

Question 62

Question
How many of the following statements are true? ◦ ECC and non-ECC memory cost the same ◦ The parity bit in parity memory can be used to reconstruct bad data ◦ ECC memory allows for the correction of single bit errors ◦ Non-parity memory can detect and correct memory errors
Answer
  • 0
  • 1
  • 2
  • 3
  • 4

Question 63

Question
How many of the following statements are true? ◦ ECC and non-ECC memory cost the same ◦ The parity bit in parity memory can be used to reconstruct bad data ◦ ECC memory allows for the correction of single bit errors ◦ Non-parity memory can detect and correct memory errors
Answer
  • Even
  • Odd

Question 64

Question
Which BUS version is set to replace AGP?
Answer
  • PCIe
  • ISA
  • Infiniband
  • PCI-X

Question 65

Question
With parity memory, the 8th bit is used to store parity for the bytes and as a result can only store a 7-bit value.
Answer
  • True
  • False

Question 66

Question
Synchronous SRAM is more expensive and about 30% slower than asynchronous SRAM.
Answer
  • True
  • False

Question 67

Question
What kind of Parity checking is being used if the following byte of data and it's parity bit are correct: Value: 1011 0111 Parity Bit: 1
Answer
  • even
  • equal
  • odd
  • balanced

Question 68

Question
Complete the following statement: _________ RAM holds data for a very short period of time and needs to be constantly refreshed, whereas _________ RAM, because of its construction, holds data until the power is turned off.
Answer
  • PRAM, DRAM
  • SRAM, DRAM
  • DRAM, SRAM
  • SRAM, PRAM

Question 69

Question
What is the name given to the automatic detection of the Manufacturer BIOS timing settings for a specific memory module via an EEPROM chip?
Answer
  • Ram Timing Detect
  • Auto-Timing Detect
  • Serial Presence Detect
  • Memory Alert

Question 70

Question
Generally speaking (and excluding Flash memory), RAM can be divided into two major categories, and those categories are static and dynamic.
Answer
  • True
  • False

Question 71

Question
You have a system board that accepts DDR266 RAM (ie. twice clock speed) but whose actual clock speed for the memory bus is 133MHz. You are using the AMD Athlon chip (Comparable to PIII). What is the approximate possible throughput of the memory bus with this combination in gigabytes per second?
Answer
  • 1.6GB/s
  • 2.1GB/s
  • 3.2GB/s
  • 1.06GB/s

Question 72

Question
One error-checking procedure for memory, whereby either every byte has an even number of ones or every byte has an odd number of ones is known as _____.
Answer
  • checksum
  • bit parity
  • ESCD
  • PRAM

Question 73

Question
What type of bus is displayed in the figure below
Image:
856a0f4c-e3fd-49c5-ac2c-fc939a0a81cb (image/jpeg)
Answer
  • 16-bit ISA
  • VESA
  • 8-bit ISA
  • PCI

Question 74

Question
The 16-bit ISA bus contains an extra ____ IRQ lines and ____ DMA channels above and beyond what is available for the 8 bit ISA Bus. (HINT: Remember DMA Channel 4 is used for the controller and not available to the bus)
Answer
  • 6,3
  • 3,6
  • 5,3
  • 5,4

Question 75

Question
Which of the following is a list of expansion bus types ?
Answer
  • MCA, PCI, Memory
  • ISA, EISA
  • ISA, PCD, AGD
  • PCI, DIMM, SIMM

Question 76

Question
The ______ ISA bus was so named because it had only an eight-bit data path.
Answer
  • 4-bit
  • 8-bit
  • 16-bit
  • 32-bit

Question 77

Question
ECC may be present on DIMM module, and correct single bit errors when possible.
Answer
  • True
  • False

Question 78

Question
DRAM SIMMs rapidly lose their data and must be refreshed every 3.86 milliseconds.
Answer
  • True
  • False

Question 79

Question
Using even parity, the computer makes the parity bit a 1 or 0 to make the number of ones in a byte _____.
Answer
  • even
  • equal
  • odd
  • balanced

Question 80

Question
All data stored in _____ is lost when the power is turned off.
Answer
  • PRAM
  • RAM
  • ROM
  • CMOS

Question 81

Question
On AGP 8x bus, the maximum throughput is ___________ (The current specs on an AGP bus are 32 bit Data Path and a 66 MHz clock)
Answer
  • 2.1 GB/s
  • 1.6 GB/s
  • 500 MB/s
  • 3.2 GB/s

Question 82

Question
The first expansion bus introduced in the 8086 processor IBM PC is called the _______ bus.
Answer
  • S-100
  • 8-bit ISA
  • 16-bit ISA
  • EISA

Question 83

Question
ECC RAM differs from parity and nonparity RAM in that it can ______.
Answer
  • retain data when the power is removed
  • detect errors
  • automatically save data to the hard drive
  • detect and potentially correct errors
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