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3367144
CPU (Central Processing Unit)
Description
Trabajo dia 04/09/15
No tags specified
trabajo
computer
science
Mind Map by
ChrisBayona1707
, updated more than 1 year ago
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Created by
ChrisBayona1707
over 9 years ago
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Resource summary
CPU (Central Processing Unit)
Parts
Control Unit (CU)
Acts as a organizing force of the computer
Is in charge of ...
Controlling the sequence of the execution of instructions
Moving information between the CPU and the Primary Memory via Data Bus
Controlling the Cache Memory
Cache Memory stores the instrucions that are used many times
Works with Special Registers
Memory Address Register (MAR)
Stores address of the data that was fetch to the CU
Stores address of where the data that was fetch to the CU is stored in the Cache Memory or in the RAM
Memory Data Register (MDR)
Stores Information that has being fetch or needs to be store inside the addresses that are store by the MAR
Both are used in the Machine Cycle
Program Counter (PC)
Contains addresses of the instructions that are going to be executed next by the IR
Instruction Register (IR)
Holds instructions that are being executed
Takes place in the Machine Cycle, by doing the process of fetching and coding
It doesn't execute instructions
Arithmetic and Logic Unit (ALU)
Performs ...
Logical operations
AND - OR - NOT
Arithmetical operations
Adding - Multiplying - Dividing - Subtracting
Receives instructions decode by the CU
Machine Cycle
Process in which a instructions is executed
4 Main Steps
1. Fetch
2. Decode
3. Execute
4.Write-Back
Done in the ALU
Outputs the executed instructions into the RAM or the Cache Memory by the use of Data Bus
Executes the instructions and gets more information if it is necessary
Done in the CU
2. Decode
Brakes the instructions into parts and sends it to the ALU by the use of Data Bus
Search for a instructions in the RAM or the Cache Memory, that comes with a Address that is save by the MAR
Can transfer information (Instructions or Addresses - Data) between them and the rest of the components in the computer by the use of Buses
Address Bus
Tranfers addresses
Data Bus
Transfers information
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